參數(shù)資料
型號(hào)： SII3124A
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁數(shù)： 38/88頁
文件大小： 621K
代理商： SII3124A
PCI-X to Serial ATA Controller
Data Sheet
5.3.11 Interlocked Receive PRB Structure
Reserving a command slot to receive an interlocked FIS is indicated by setting control_receive (control field, bit 3). To receive
an interlocked FIS into host memory, the host driver first specifies the FIS type(s) to be interlocked by writing the appropriate
value to the FIS Configuration register (port registers, offset 0x1028). The PRB is populated with SGEs that define the host
memory region(s) that will be used to receive the interlocked FIS. When a FIS of the defined type is received, it will be written
to the defined host memory area and the command will be completed. If an error occurs during receipt of the FIS, or the SGEs
define an area that is not large enough to contain the entire FIS, the FIS will be rejected with an R_ERR response and the
command will not complete. When an interlocked FIS is received without error into a memory region that is large enough to
contain it, the command will be successfully completed and the host driver may use the received FIS in any manner. The
command slot is then free to be redefined as a receive slot or as any other command type.
After successfully receiving an interlocked FIS, the low-level link will be receiving WTRM primitives from the transmitting
device, which is expecting a response. By default, the SiI3124 waits for the host driver to write a response bit to the port
control register. If the host driver writes Interlock Accept (Port Control Set register, bit 12), an R_OK response will be
transmitted. If the host driver writes Interlock Reject (Port Control Set register, bit 11), an R_ERR response will be transmitted.
The host driver may also elect to set Auto Interlock Accept (Port Control Set register, bit 14) before performing interlocked
operations. Setting this bit will cause an R_OK response to be sent for all subsequently received interlocked FISes, without
additional intervention from the host driver. It should be noted that in this mode, it is possible to receive one or more additional
interlocked FISes before the host driver has had a chance to reserve command slots to receive them. If this occurs, any
interlocked FIS that arrives without a reserved slot available will be acknowledged and discarded.
31
Protocol Override
Received Transfer Count
Reserved – Must Be Zero
SGE0 Data Address Low
SGE0 Data Address High
SGE0 Data Count
SGE0 TRM
SGE0 LNK
SGE0 DRD
SGE0 XCF
SGE1 Data Address Low
SGE1 Data Address High
SGE1 Data Count
SGE1 TRM
SGE1 LNK
SGE1 DRD
SGE1 XCF
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
38
0
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Control
Reserved[27:0]
Reserved[27:0]
Table 5-10 Port Request Block For Receiving Interlocked FIS
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