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參數(shù)資料
| 型號(hào)： | SII3124A |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI-X to Serial ATA Controller |
| 中文描述： | PCI - X到串行ATA控制器 |
| 文件頁(yè)數(shù)： | 75/88頁(yè) |
| 文件大?。?/td> | 621K |
| 代理商： | SII3124A |
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PCI-X to Serial ATA Controller
Silicon Image, Inc.
7.3.11 Port FIS Configuration
Address Offset: 1028
H
Access Type: Read/Write
Reset Value: 0x1000_1555
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
75
R
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
This register contains bits for controlling Serial ATA FIS reception. For each possible FIS type, a 2-bit code defines the
desired reception behavior as follows:
00 – Accept FIS without interlock.
01 – Reject FIS without interlock
10 – Interlock FIS. Receive FIS into slot reserved for interlocked FIS reception. If no slot has been reserved,
reject the FIS.
11 – Reserved.
Bit[1:0] (FISOcfg) defines the 2-bit code for all other FIS types not defined by bits [29:2].
The following table defines the default behavior of FIS configuration.
Table 7-8 Default FIS Configurations
Configuration Bits
FIS
Code
FIS Name
Signals
fis27cfg[1:0]
fis34cfg[1:0]
fis39cfg[1:0]
fis41cfg[1:0]
fis46cfg[1:0]
fis58cfg[1:0]
fis5Fcfg[1:0]
fisa1cfg[1:0]
fisa6cfg[1:0]
fisb8cfg[1:0]
fisbFcfg[1:0]
fisc7cfg[1:0]
fisd4cfg[1:0]
fisd9cfg[1:0]
fisocfg[1:0]
Default
Value
01b
00b
00b
00b
00b
00b
00b
00b
01b
01b
01b
01b
01b
01b
01b
Default Action
27h
34h
39h
41h
46h
58h
5Fh
A1h
A6h
B8h
BFh
C7h
D4h
D9h
Others
Register (Host to Device)
Register (Device to Host)
DMA Activate
DMA Setup
Data
BIST Activate
PIO Setup
Set Device Bits
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reject FIS without interlock
accept FIS without interlock
accept FIS without interlock
accept FIS without interlock
accept FIS without interlock
accept far-end retimed loopback, reject any other
accept FIS without interlock
accept FIS without interlock
reject FIS without interlock
reject FIS without interlock
reject FIS without interlock
reject FIS without interlock
reject FIS without interlock
reject FIS without interlock
reject FIS without interlock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SiI3124ACBHU | PCI-X to Serial ATA Controller |
| SII3132 | PCI Express to 2-Port Serial ATA II Host Controller |
| SII3512 | PCI to Serial ATA Controller |
| SiI3512ECTU128 | PCI to Serial ATA Controller |
| SII3531A | PCI Express to Serial ATA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
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