- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄365566 > SiI3114 (Silicon Image, Inc.) PCI to Serial ATA Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | SiI3114 |
| 廠(chǎng)商： | Silicon Image, Inc. |
| 英文描述： | PCI to Serial ATA Controller |
| 中文描述： | PCI到Serial ATA控制器 |
| 文件頁(yè)數(shù)： | 65/127頁(yè) |
| 文件大?。?/td> | 598K |
| 代理商： | SII3114 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)當(dāng)前第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
57
SiI
-DS-0103-D
FIFO Valid Byte Count and Control – Channel
X
Address Offset: 40
H
/ 44
H
/ 240
H
/ 244
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
FIFO Valid Byte Count
Reserved
FIFO Wr
Req Ctrl
Reserved
FIFO Rd
Req Ctrl
This register defines the FIFO valid byte count register and PCI bus request control for Channel
X
in the
SiI
3114.
The register bits are defined below.
The FIFO Write Request Control and FIFO Read Request Control fields in these registers provide threshold
settings for establishing when PCI requests are made to the Arbiter. The Arbiter arbitrates among the four
requests using fixed priority with masking. The fixed priority is, from highest to lowest: channel 0; channel 1;
channel 2; and channel 3. If multiple requests are present, the arbiter grants PCI bus access to the highest
priority channel that is not masked. That channel’s request is then masked as long as any unmasked requests are
present.
Bit [31:25]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [24:16]
: FIFO Valid Byte Count (R). This bit field provides the valid byte count for the data FIFO for
Channel
X
. A value of 000
H
indicates empty, while a value of 100
H
indicates a full FIFO with 256 bytes.
Bit [15:11]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [10:08]
: FIFO Wr Req Ctrl (R/W) – FIFO Write Request Control. This bit field defines the FIFO
threshold to assign priority when requesting a PCI bus write operation. A value of 00
H
indicates that write
request priority is set whenever the FIFO contains greater than 32 bytes, while a value of 07
H
indicates that
write request priority is set whenever the FIFO contains greater than 7x32 bytes (=224 bytes). This bit field
is useful when multiple DMA channels are competing for the PCI bus.
Bit [07:03]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [02:00]
: FIFO Rd Req Ctrl (R/W) – FIFO Read Request Control. This bit field defines the FIFO
threshold to assign priority when requesting a PCI bus read operation. A value of 00
H
indicates that read
request priority is set whenever the FIFO has greater than 32 bytes available space, while a value of 07
H
indicates that read request priority is set whenever the FIFO has greater than 7x32 bytes (=224 bytes)
available space. This bit field is useful when multiple DMA channels are competing for accessing the PCI
bus.
System Configuration Status – Command
Address Offset: 48
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
C
C
C
C
Reserved
M
Reserved
C
C
F
F
C
C
F
F
R
A
P
This register defines the system configuration status and command register for the
SiI
3114. The register bits are
defined below.
Bit [31:26]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [25]
: Chnl3 Int Block (R/W) – Channel3 Interrupt Block. This bit is set to block interrupts from Channel
3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3114_07 | PCI to Serial ATA Controller |
| SiI3114CT176 | PCI to Serial ATA Controller |
| SiI3114CTU | PCI to Serial ATA Controller |
| SII3124A | PCI-X to Serial ATA Controller |
| SiI3124ACBHU | PCI-X to Serial ATA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3114_07 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3114CT176 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。