參數(shù)資料
型號： SiI3114
廠商： Silicon Image, Inc.
英文描述： PCI to Serial ATA Controller
中文描述： PCI到Serial ATA控制器
文件頁數(shù)： 42/127頁
文件大?。?/td> 598K
代理商： SII3114
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI
-DS-0103-D
34
2007 Silicon Image, Inc.
Power Management Control + Status
Address Offset: 64
H
Access Type: Read/Write
Reset Value: 0x6400_4000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
P
P
PPM Data Sel
P
Reserved
P
This register defines the power management capabilities associated with the PCI bus. The register bits are
defined below.
Bit [31:24]
: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 0x64.
Bit [23:16]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]
:
PME Status (R) – PME Status. This bit is hardwired to 0. The
SiI
3114 does not support PME.
Bit [14:13]
:
PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 10
B
to
indicate a scaling factor of 10 mW.
Bit [12:09]
:
PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system
to indicate which data field is to be reported through the PPM Data bits (although current implementation
hardwires the PPM Data to indicate 1 Watt).
Bit [08]
:
PME Ena (R) – PME Enable. This bit is hardwired to 0. The
SiI
3114 does not support PME.
Bit [07:02]
:
Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]
:
PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the
system to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3
(Hot).
PCI Bus Master – Channel 0/2
Address Offset: 70
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
P
P
R
D
P
P
Reserved
Reserved
P
R
P
This register defines the PCI bus master register for Channel 0/2 in the
SiI
3114. The register bits are also
mapped to Base Address 4, Offset 00
H
, Base Address 5, Offset 00
H
, and Base Address 5, Offset 10
H
(Note that
these registers are, however, not identical). See “PCI Bus Master – Channel
X
” section on page 53 for bit
definitions.
相關(guān)PDF資料
PDF描述
SII3114_07 PCI to Serial ATA Controller
SiI3114CT176 PCI to Serial ATA Controller
SiI3114CTU PCI to Serial ATA Controller
SII3124A PCI-X to Serial ATA Controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3114_07 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller
SII3114CT176 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller
SII3114CTU 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述:
SII3124A 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3124ACBHU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
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