
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Register Definitions
2007 Silicon Image, Inc.
25
SiI
-DS-0103-D
This section describes the registers within the
SiI
3114.
PCI Configuration Space
The PCI Configuration Space registers define he operation of the
SiI
3114 on the PCI bus. These registers are
accessible only when the
SiI
3114 detects a Configuration Read or Write operation, with its IDSEL asserted, on
the 32-bit PCI bus. Table 16 outlines the PCI Configuration space for the
SiI
3114.
Table 16.
SiI
3114 PCI Configuration Space
Register Name
Address
Offset
31 16
Device ID
PCI Status
15 00
Vendor ID
PCI Command
Access
Type
00
H
04
H
08
H
0C
H
10
H
14
H
18
H
1C
H
20
H
24
H
28
H
2C
H
30
H
34
H
38
H
3C
H
40
H
44
H
48
H
4C
H
50
H
54
H
58
H
5C
H
60
H
64
H
68
H
6C
H
70
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R
R/W
R/W
R/W
R/W
-
-
-
-
-
-
R/W
R/W
-
-
R/W
PCI Class Code
Header Type
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Reserved
Subsystem ID
Expansion ROM Base Address
Reserved
Revision ID
Cache Line Size
BIST
Latency Timer
Subsystem Vendor ID
Capabilities Ptr
Reserved
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
Configuration
Reserved
Software Data Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Power Management Capabilities
Data
Next Item Pointer
Functions Control and Status
Reserved
Reserved
PCI Bus Master
Status – Channel
0/2
PRD Table Address – Channel 0/2
PCI Bus Master
Status – Channel
1/3
PRD Table Address – Channel 1/3
Reserved
Capability ID
Reserved
Reserved
Reserved
PCI Bus Master
Command –
Channel 0/2
74
H
78
H
R/W
R/W
Reserved
Reserved
PCI Bus Master
Command –
Channel 1/3
7C
H
80
H
R/W
R/W
Channel 0/2 Data
Transfer Mode