
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SATA Interface Transmitter Output Jitter Characteristics
SiI
-DS-0103-D
6
2007 Silicon Image, Inc.
Table 5. SATA Interface Transmitter Output Jitter Characteristics
Limits
Typ
Symbol
Parameter
Condition
Min
Max
Unit
RJ
5UI
5UI later Random Jitter
Measured at Tx output pins
1sigma deviation
Measured at Tx output pins
1sigma deviation
Measured at Tx output pins peak
to peak phase variation Random
data pattern
-
4.5
-
ps rms
RJ
250UI
250UI later Random
Jitter
5UI later Deterministic
Jitter
-
6.0
-
ps rms
DJ
5UI
-
40
-
ps
DJ
250UI
250UI later Deterministic
Jitter
Measured at Tx output pins peak
to peak phase variation Random
data pattern
-
45
-
ps
CLKI SerDes Reference Clock Input Requirements
Table 6. CLKI SerDes Reference Clock Input Requirements
Limits
Typ
25
100
-
Symbol
Parameter
Condition
Min
-
Max
-
Unit
T
CLKI_FREQ
Nominal Frequency
REXT = 1k 1%
REXT = 4.99k 1%
-
MHz
V
CLK_IH
V
CLK_IL
T
CLKI_J
T
CLKI_RISE_FALL
Rise and Fall time at CLKI
Input High Voltage
0.7xVDDX
-
V
Input Low Voltage
CLKI frequency tolerance
-
-
25MHz reference clock,
20%-80%
100MHz reference clock,
20%-80%
20%-80%
-
-
-
0.3xVDDX
+100
4
2
V
-100
-
ppm
ns
T
CLKI_RC_DUTY
CLKI duty cycle
Notes: CLKI must be 1.8V swing when external clock input to this pin
PCI 33 MHz Timing Specifications
40
-
60
%
Table 7. PCI 33 MHz Timing Specifications
Limits
Symbol
Parameter
Min
2.0
2.0
2.0
-
7.0
10.0
0.0
Max
11.0
11.0
-
28.0
-
-
-
Unit
T
VAL
T
VAL
(PTP)
T
ON
T
OFF
T
SU
T
SU (PTP)
T
H
CLK to Signal Valid – Bussed Signals
CLK to Signal Valid – Point to Point
Float to Active Delay
Active to Float Delay
Input Setup Time – Bussed Signals
Input Setup Time – Point to Point
Input Hold Time
ns
ns
ns
ns
ns
ns
ns