參數資料
型號: SC16C752IB48,157
廠商: NXP Semiconductors
文件頁數: 46/47頁
文件大?。?/td> 0K
描述: IC DUAL UART 64BYTE 48LQFP
標準包裝: 1,250
通道數: 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 935270055157
SC16C752IB48
SC16C752IB48-ND
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
8 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.2.1
Auto-RTS
Auto-RTS data ow control originates in the receiver block (see Figure 1 “Block
diagram.” on page 3). Figure 4 shows RTS functional timing. The receiver FIFO
trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger
level is reached, RTS is deasserted. The sending device (e.g., another UART) may
send an additional byte after the trigger level is reached (assuming the sending UART
has another byte to send) because it may not recognize the deassertion of RTS until
it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This
reassertion allows the sending device to resume transmission.
6.2.2
Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be deasserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system.
When ow control is enabled, CTS level changes do not trigger host interrupts
because the device automatically controls its own transmitter. Without auto-CTS, the
transmitter sends any data present in the transmit FIFO and a receiver overrun error
may result.
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.
Fig 4.
RTS functional timing.
START
BYTE N
START
BYTE N + 1
START
STOP
RX
RTS
IOR
N
N+1
12
002aaa226
(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter nishes sending the current
byte, but is does not send the next byte.
(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 5.
CTS functional timing.
START
BYTE 0-7
STOP
TX
CTS
002aaa227
START
BYTE 0-7
STOP
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