參數(shù)資料
型號： SC16C752IB48,157
廠商： NXP Semiconductors
文件頁數(shù)： 16/47頁
文件大?。?/td> 0K
描述： IC DUAL UART 64BYTE 48LQFP
標準包裝： 1,250
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
其它名稱： 935270055157
SC16C752IB48
SC16C752IB48-ND
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
23 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.5 Line status register (LSR)
Table 13 shows the line status register bit settings.
When the LSR is read, LSR[4:2] reect the error bits (BI, FE, PE) of the character at
the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the RX FIFO is output directly onto the output
data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identied
by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer. The
RX FIFO read pointer is incremented by reading the RHR.
Table 13:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error, or break indication is
in the receiver FIFO. This bit is cleared when no more errors are
present in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
Logic 0 = Transmitter hold and shift registers are not empty.
Logic 1 = Transmitter hold and shift registers are empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
Logic 0 = Transmit hold register is not empty.
Logic 1 = Transmit hold register is empty. The processor can now load
up to 64 bytes of data into the THR if the TX FIFO is enabled.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic1=A break condition occurred and associated byte is 00, i.e.,
RX was LOW for one character time frame.
3
LSR[3]
Framing error.
Logic 0 = No framing error in data being read from RX FIFO (normal
default condition).
Logic1=Framing error occurred in data being read from RX FIFO, i.e.,
received data did not have a valid stop bit.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error in data being read from RX FIFO.
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error has occurred.
0
LSR[0]
Data in receiver.
Logic 0 = No data in receive FIFO (normal default condition).
Logic 1 = At least one character in the RX FIFO.
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