參數(shù)資料
型號: SC16C752IB48,157
廠商: NXP Semiconductors
文件頁數(shù): 3/47頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
標(biāo)準(zhǔn)包裝: 1,250
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 935270055157
SC16C752IB48
SC16C752IB48-ND
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
11 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
60 characters have been sent. At this time, UART2 will transmit a 0F to UART1,
informing UART1 to halt transmission. UART1 will likely send the 61st character while
UART2 is sending the Xoff character. Now UART2 is serviced and the processor
reads enough data out of the RX FIFO that the level drops to 32. UART2 will now
send a 0D to UART1, informing UART1 to resume transmission.
6.4 Reset
Table 4 summarizes the state of register after reset.
[1]
Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal
RESET, i.e., they hold their initialization values during reset.
Table 5 summarizes the state of registers after reset.
Table 4:
Register reset functions
Register
Reset control
Reset state
Interrupt enable register
RESET
All bits cleared.
Interrupt identication register
RESET
Bit 0 is set. All other bits cleared.
FIFO control register
RESET
All bits cleared.
Line control register
RESET
Reset to 00011101 (1D hex).
Modem control register
RESET
All bits cleared.
Line status register
RESET
Bits 5 and 6 set. All other bits cleared.
Modem status register
RESET
Bits 0-3 cleared. Bits 4-7 input signals.
Enhanced feature register
RESET
All bits cleared.
Receiver holding register
RESET
Pointer logic cleared.
Transmitter holding register
RESET
Pointer logic cleared.
Transmission control register
RESET
All bits cleared.
Trigger level register
RESET
All bits cleared.
Table 5:
Signal RESET functions
Signal
Reset control
Reset state
TX
RESET
high
RTS
RESET
high
DTR
RESET
high
RXRDY
RESET
high
TXRDY
RESET
low
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