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參數(shù)資料
| 型號： | SC16C752IB48,157 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL UART 64BYTE 48LQFP |
| 標準包裝： | 1,250 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 935270055157 SC16C752IB48 SC16C752IB48-ND |
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Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
28 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.11 Divisor latches (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud
clock in the baud rate generator. DLH stores the most signicant part of the divisor.
DLL stores the least signicant part of the divisor.
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e.,
before IER[4] is set.
7.12 Transmission control register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start
transmission during hardware/software ow control. Table 20 shows transmission
control register bit settings.
TCR trigger levels are available from 0-60 bytes with a granularity of four.
Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The
programmer must program the TCR such that TCR[3:0] > TCR{7:4]. There is no
built-in hardware check to make sure this condition is met. Also, the TCR must be
programmed with this condition before Auto-RTS or software ow control is enabled
to avoid spurious operation of the device.
7.13 Trigger level register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels
used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed
with a granularity of 4. Table 21 shows trigger level register bit settings.
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60
bytes are available with a granularity of four. The TLR should be programmed for N
4,
where N is the desired trigger level.
When the trigger level setting in TLR is zero, the SC16C752 uses the trigger level
setting dened in FCR. If TLR has non-zero trigger level value, the trigger level
dened in FCR is discarded. This applies to both transmit FIFO and receive FIFO
trigger level setting.
When TLR is used for RX trigger level control, ICR[7:6] should be left at the default
state, i.e., ‘00’.
Table 20:
Transmission Control Register bits description
Bit
Symbol
Description
7-4
TCR[7:4]
RX FIFO trigger level to resume transmission (0-60).
3-0
TCR[3:0]
RX FIFO trigger level to halt transmission (0-60).
Table 21:
Trigger Level Register bits description
Bit
Symbol
Description
7-4
TLR[7:4]
RX FIFO trigger levels (4-60), number of characters available.
3-0
TLR[3:0]
TX FIFO trigger levels (4-60), number of spaces available.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C754 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad UART with 64-byte FIFO |
| SC16C754B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs |
| SC16C754BIA68 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,512 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,518 | 功能描述:UART 接口集成電路 4CH. UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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