參數(shù)資料
型號: SC16C752IB48,157
廠商: NXP Semiconductors
文件頁數(shù): 18/47頁
文件大?。?/td> 0K
描述: IC DUAL UART 64BYTE 48LQFP
標(biāo)準(zhǔn)包裝: 1,250
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 935270055157
SC16C752IB48
SC16C752IB48-ND
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
25 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.7 Modem status register (MSR)
This 8-bit register provides information about the current state of the control lines
from the mode, data set, or peripheral device to the processor. It also indicates when
a control input from the modem changes state. Table 15 shows modem status
register bit settings per channel.
[1]
The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR
and MCR (in loop-back) registers are Active-HIGH.
7.8 Interrupt enable register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from
LOW to HIGH. The INT output signal is activated in response to interrupt generation.
Table 16 shows interrupt enable register bit settings.
Table 15:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (Active-HIGH, logical 1). This bit is the complement of the CD input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[3].
6
MSR[6]
RI (Active-HIGH, logical 1). This bit is the complement of the RI input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[2].
5
MSR[5]
DSR (Active-HIGH, logical 1). This bit is the complement of the DSR
input during normal mode. During internal loop-back mode, it is
equivalent MCR[0].
4
MSR[4]
CTS (Active-HIGH, logical 1). This bit is the complement of the CTS
input during normal mode. During internal loop-back mode, it is
equivalent to MCR[1].
3
MSR[3]
CD. Indicates that CD input (or MCR[3] in loop-back mode) has
changed state. Cleared on a read.
2
MSR[2]
RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed
state from LOW to HIGH. Cleared on a read.
1
MSR[1]
DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has
changed state. Cleared on a read.
0
MSR[0]
CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has
changed state. Cleared on a read.
Table 16:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7] [1]
CTS interrupt enable.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt.
6
IER[6] [1]
RTS interrupt enable.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt.
5
IER[5] [1]
Xoff interrupt.
Logic 0 = Disable the Xoff interrupt (normal default condition).
Logic 1 = Enable the Xoff interrupt.
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