參數(shù)資料
型號: SC16C752IB48,157
廠商: NXP Semiconductors
文件頁數(shù): 19/47頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
標準包裝: 1,250
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 935270055157
SC16C752IB48
SC16C752IB48-ND
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
26 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
IER[7:4] can only be modied if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will
not cause a new interrupt if the THR is below the threshold.
7.9 Interrupt identication register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 17 shows interrupt identication register bit settings.
The interrupt priority list is shown in Table 18.
4
IER[4] [1]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See Section 6.7 “Sleep mode” for details.
3
IER[3]
Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
2
IER[2]
Receive Line Status interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
1
IER[1]
Transmit Holding Register interrupt.
Logic 0 = Disable the THR interrupt (normal default condition).
Logic 1 = Enable the THR interrupt.
0
IER[0]
Receive Holding Register interrupt.
Logic 0 = Disable the RHR interrupt (normal default condition).
Logic 1 = Enable the RHR interrupt.
Table 16:
Interrupt Enable Register bits description…continued
Bit
Symbol
Description
Table 17:
Interrupt Identication Register bits description
Bit
Symbol
Description
7-6
IIR[7:6]
Mirror the contents of FCR[0].
5
IIR[5]
RTS/CTS LOW-to-HIGH change of state.
4
IIR[4]
1 = Xoff/Special character has been detected.
3-1
IIR[3:1]
3-bit encoded interrupt. See Table 18.
0
IIR[0]
Interrupt status.
Logic 0 = An interrupt is pending.
Logic 1 = No interrupt is pending.
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