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參數(shù)資料
| 型號(hào)： | SC1200 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory |
| 中文描述： | 精密模擬到數(shù)字轉(zhuǎn)換器（ADC）和數(shù)字到模擬轉(zhuǎn)換器（DAC）的8051微控制器和閃存 |
| 文件頁(yè)數(shù)： | 57/60頁(yè) |
| 文件大小： | 802K |
| 代理商： | SC1200 |
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MSC1200
SBAS289E
57
www.ti.com
FREQ5-0
bits 5-0
Clock Frequency
–
1.
This value + 1 divides the system clock to create a 1
μ
s Clock.
USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EF
H
).
One Millisecond Low Register (MSECL)
MSECL7-0
bits 7-0
One Millisecond Low.
This value in combination with the next register is used to create a 1ms Clock.
1ms Clock = (MSECH
256 + MSECL + 1)
t
CLK
. This clock is used to set Flash erase time. See FTCON (SFR EF
H
).
One Millisecond High Register (MSECH)
7
6
5
4
3
2
1
0
Reset Value
SFR FB
H
0
0
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03
H
7
6
5
4
3
2
1
0
Reset Value
SFR FD
H
MSECH7
MSECH6
MSECH5
MSECH4
MSECH3
MSECH2
MSECH1
MSECH0
0F
H
7
6
5
4
3
2
1
0
Reset Value
SFR FC
H
MSECL7
MSECL6
MSECL5
MSECL4
MSECL3
MSECL2
MSECL1
MSECL0
9F
H
MSECH7-0
bits 7-0
One Millisecond High.
This value in combination with the previous register is used to create a 1ms clock.
1ms = (MSECH
256 + MSECL + 1)
t
CLK
.
One Hundred Millisecond Register (HMSEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FE
H
HMSEC7
HMSEC6
HMSEC5
HMSEC4
HMSEC3
HMSEC2
HMSEC1
HMSEC0
63
H
7
6
5
4
3
2
1
0
Reset Value
SFR FF
H
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
00
H
HMSEC7-0
bits 7-0
One Hundred Millisecond.
This clock divides the 1ms clock to create a 100ms clock.
100ms = (MSECH
256 + MSECL + 1)
(HMSEC + 1)
t
CLK
.
Watchdog Timer Register (WDTCON)
EWDT
bit 7
Enable Watchdog (R/W).
Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT
bit 6
Disable Watchdog (R/W).
Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT
bit 5
Reset Watchdog (R/W).
Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4-0
bits 4-0
Watchdog Count (R/W).
Watchdog expires in (WDCNT + 1)
HMSEC to (WDCNT + 2)
HMSEC, if the sequence is not asserted. There
is an uncertainty of 1 count.
NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared
and the watchdog timer expires, an interrupt is generated (see Table VII).
One Microsecond Register (USEC)
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