參數(shù)資料
型號(hào)： SC1200
廠商： Texas Instruments, Inc.
英文描述： Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory
中文描述： 精密模擬到數(shù)字轉(zhuǎn)換器（ADC）和數(shù)字到模擬轉(zhuǎn)換器（DAC）的8051微控制器和閃存
文件頁(yè)數(shù)： 56/60頁(yè)
文件大?。?/td> 802K
代理商： SC1200
MSC1200
SBAS289E
56
www.ti.com
The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL.
Reading this register will clear MSINT.
WRT
bit 7
Write Control.
Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
MSINT6-0
bits 6-0
Seconds Count.
Normal operation would use 1ms as the clock interval.
MS Interrupt Interval = (1 + MSINT)
(MSEC + 1)
t
CLK
7
6
5
4
3
2
1
0
Reset Value
SFR FA
H
WRT
MSINT6
MSINT5
MSINT4
MSINT3
MSINT2
MSINT1
MSINT0
7F
H
Milliseconds Interrupt (MSINT)
7
6
5
4
3
2
1
0
Reset Value
SFR F8
H
1
1
1
PWDI
PX5
PX4
PX3
PX2
E0
H
7
6
5
4
3
2
1
0
Reset Value
SFR F9
H
WRT
SECINT6
SECINT5
SECINT4
SECINT3
SECINT2
SECINT1
SECINT0
7F
H
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then that 1ms timer tick is divided by the register
HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt
which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored
in the AIE register.
WRT
bit 7
Write Control.
Determines whether to write the value immediately or wait until the current count is finished.
Read = 0.
0 = Delay Write Operation. The SEC value is loaded when the current count expires.
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT6-0 Seconds Count.
Normal operation would use 100ms as the clock interval.
bits 6-0
Seconds Interrupt = (1 + SEC)
(HMSEC + 1)
(MSEC + 1)
t
CLK
.
PWDI
bit 4
Watchdog Interrupt Priority.
This bit controls the priority of the watchdog interrupt.
0 = The watchdog interrupt is low priority.
1 = The watchdog interrupt is high priority.
PX5
bit 3
External Interrupt 5 Priority.
This bit controls the priority of external interrupt 5.
0 = External interrupt 5 is low priority.
1 = External interrupt 5 is high priority.
PX4
bit 2
External Interrupt 4 Priority.
This bit controls the priority of external interrupt 4.
0 = External interrupt 4 is low priority.
1 = External interrupt 4 is high priority.
PX3
bit 1
External Interrupt 3 Priority.
This bit controls the priority of external interrupt 3.
0 = External interrupt 3 is low priority.
1 = External interrupt 3 is high priority.
PX2
bit 0
External Interrupt 2 Priority.
This bit controls the priority of external interrupt 2.
0 = External interrupt 2 is low priority.
1 = External interrupt 2 is high priority.
Seconds Timer Interrupt (SECINT)
Extended Interrupt Priority (EIP)
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