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參數(shù)資料
| 型號： | SC1200 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory |
| 中文描述： | 精密模擬到數(shù)字轉(zhuǎn)換器（ADC）和數(shù)字到模擬轉(zhuǎn)換器（DAC）的8051微控制器和閃存 |
| 文件頁數(shù)： | 51/60頁 |
| 文件大?。?/td> | 802K |
| 代理商： | SC1200 |
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MSC1200
SBAS289E
51
www.ti.com
SHF2-0
bits 2-0
Shift Count.
SUMR0
bits 7-0
Summation Register 0.
This is the least significant byte of the 32-bit summation register or bits 0 to 7.
Write: will cause values in SUMR3-0 to be added to or subtracted from the summation register.
Read: will clear the Summation Interrupt.
Summation Register 1 (SUMR1)
SHF2
SHF1
SHF0
SHIFT
DIVIDE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
2
4
8
16
32
64
128
256
7
6
5
4
3
2
1
0
Reset Value
SFR E2
H
LSB
00
H
SUMR1
bits 7-0
Summation Register 1.
This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15.
Summation Register 2 (SUMR2)
7
6
5
4
3
2
1
0
Reset Value
SFR E3
H
00
H
SUMR2
bits 7-0
Summation Register 2.
This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23.
7
6
5
4
3
2
1
0
Reset Value
SFR E4
H
00
H
SSCON1-0 Summation/Shift Control.
bits 7-6
SSCON1 SSCON0
SCNT2-0
bits 5-3
Summation Count.
When the summation is complete an interrupt will be generated unless masked. Reading the
SUMR0 register clears the interrupt.
SCNT2
SCNT1 SCNT0
SUMMATION COUNT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
DESCRIPTION
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
x
0
1
0
x
0
0
0
x
0
0
0
0
0
0
0
0
0
Clear Summation Register
CPU Summation on Write to SUMR0
CPU Subtraction on Write to SUMR0
CPU Shift Only
ADC Summation Only
ADC Summation Completes then Shift Completes
Note (1)
x
Note (1)
Note (1)
x
Note (1)
Note (1)
x
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
NOTES: (1) Refer to register bit definition.
7
6
5
4
3
2
1
0
Reset Value
SFR E5
H
MSB
00
H
Summation Register 3 (SUMR3)
SUMR3
bits 7-0
Summation Register 3.
This is the most significant byte of the 32-bit summation register or bits 24-31.
Summation Register 0 (SUMR0)
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