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參數(shù)資料
| 型號： | SC1200 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory |
| 中文描述： | 精密模擬到數(shù)字轉換器（ADC）和數(shù)字到模擬轉換器（DAC）的8051微控制器和閃存 |
| 文件頁數(shù)： | 50/60頁 |
| 文件大?。?/td> | 802K |
| 代理商： | SC1200 |
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MSC1200
SBAS289E
50
www.ti.com
SM1
SM0
SETTLING MODE
0
0
1
1
0
1
0
1
Auto
Fast Settling Filter
Sinc
2
Filter
Sinc
3
Filter
ADC Control Register 1 (ADCON1)
OF_UF
bit 7
POL
bit 6
Overflow/Underflow.
If this bit is set, the data in the summation register is invalid. Either an overflow or an
underflow occurred. The bit is cleared by writing a 0 to it.
Polarity.
Polarity of the ADC result and Summation register.
0 = Bipolar.
1 = Unipolar.
7
6
5
4
3
2
1
0
Reset Value
SFR DD
H
OF_UF
POL
SM1
SM0
—
CAL2
CAL1
CAL0
x000 0000
B
POL
ANALOG INPUT
DIGITAL OUTPUT
+FSR
ZERO
–
FSR
0x7FFFFF
0x000000
0x800000
0
+FSR
ZERO
–
FSR
0xFFFFFF
0x000000
0x000000
1
SM1-0
bits 5-4
Settling Mode.
Selects the type of filter or auto select which defines the digital filter settling characteristics.
CAL2-0
bits 2-0
Calibration Mode Control Bits.
Writing to this register initiates calibration.
ADC Control Register 2 (ADCON2)
CAL2
CAL1
CAL0
CALIBRATION MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Calibration (default)
Self Calibration, Offset and Gain
Self Calibration, Offset Only
Self Calibration, Gain Only
System Calibration, Offset Only
System Calibration, Gain Only
Reserved
Reserved
DR7-0
bits 7-0
ADC Control Register 3 (ADCON3)
Decimation Ratio LSB (refer to ADCON3, SFR DF
H
).
7
6
5
4
3
2
1
0
Reset Value
SFR DE
H
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1B
H
DR10-8
bits 2-0
Accumulator (A or ACC)
Decimation Ratio Most Significant 3 Bits.
The output data rate =
f
DecimationRatio
MOD
where f
MOD
=
f
ACLK
CLK
+
(
)
1
64
.
7
6
5
4
3
2
1
0
Reset Value
SFR E0
H
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00
H
ACC.7-0
bits 7-0
Summation/Shifter Control (SSCON)
Accumulator.
This register serves as the accumulator for arithmetic and logic operations.
7
6
5
4
3
2
1
0
Reset Value
SFR E1
H
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00
H
Read Value
—
000
B
.
7
6
5
4
3
2
1
0
Reset Value
SFR DF
H
—
—
—
—
—
DR10
DR9
DR8
06
H
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit
SUMR3-0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1.
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