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參數(shù)資料
| 型號： | SC1200 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory |
| 中文描述： | 精密模擬到數(shù)字轉(zhuǎn)換器（ADC）和數(shù)字到模擬轉(zhuǎn)換器（DAC）的8051微控制器和閃存 |
| 文件頁數(shù)： | 26/60頁 |
| 文件大?。?/td> | 802K |
| 代理商： | SC1200 |
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MSC1200
SBAS289E
26
www.ti.com
Working Registers
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 20. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0 through
R7. Since there are four banks, the currently selected bank will
be used by any instruction using R0-R7. This allows software
to change context by simply switching banks. This is controlled
via the Program Status Word register (PSW; 0D0
H
) in the SFR
area described below. The 16 bytes immediately above the
R0-R7 registers are bit addressable. So any of the 128 bits in
this area can be directly accessed using bit addressable
instructions.
Stack
Another use of the Scratchpad area is for the programmer
’
s
stack. This area is selected using the Stack Pointer (SP; 81
H
)
SFR. Whenever a call or interrupt is invoked, the return
address is placed on the Stack. It also is available to the
programmer for variables, etc., since the Stack can be
moved and there is no fixed location within the RAM desig-
nated as Stack. The Stack Pointer will default to 07
H
on reset.
The user can then move it as needed. The SP will point to the
last used value. Therefore, the next value placed on the
Stack is put at SP + 1. Each PUSH or CALL will increment
the SP by the appropriate value. Each POP or RET will
decrement as well.
Program Memory
After reset, the CPU begins execution from Program Memory
location 0000
H
. The standard internal Program Memory size for
MSC1200 family members is shown in Table V. If enabled the
Boot ROM will appear from address F800
H
to FBFF
H
.
STANDARD INTERNAL
PROGRAM MEMORY SIZE (BYTES)
MODEL NUMBER
MSC1200Y3
MSC1200Y2
8k
4k
TABLE V. MSC1200 Maximum Internal Program Memory Sizes.
Boot ROM
There is a 1kB Boot ROM that controls operation during serial
programming. Additionally, the Boot ROM routines shown in
Table VI can be accessed during the user mode if it is enabled.
When enabled, the Boot ROM routines will be located at
memory addresses F800
H
-FBFF
H
during user mode.
HEX ADDRESS
ROUTINE
C DECLARATIONS
DESCRIPTION
F802
F805
FBD8
FBDA
FBDC
FBDE
FBE0
FBE2
FBE4
FBE6
FBE8
FBEA
FBEC
FBEE
FBF0
FBF2
FBF4
FBF6
FBF8
FBFA
FBFC
FBFE
sfr_rd
sfr_wr
monitor_isr
cmd_parser
put_string
page_erase
write_flash
write_flash_chk
write_flash_byte
faddr_data_read
data_x_c_read
tx_byte
tx_hex
putx
rx_byte
rx_byte_echo
rx_hex_echo
rx_hex_dbl_echo
rx_hex_word_echo
autobaud
putspace1
putcr
char sfr_rd(void);
void sfr_wr(char d);
void monitor_isr() interrupt 6;
void cmd_parser(void);
void put_string(char code *string);
char page_erase (int faddr, char fdata, char fdm);
Assembly only; DPTR = address, ACC = data
char write_flash_chk (int faddr, char fdata, char fdm);
void write_flash_byte (int faddr, char fdata);
char faddr_data_read(char faddr);
char data_x_c_read(int faddr, char fdm);
void tx_byte(char);
void tx_hex(char);
void putx(char);
char rx_byte(void);
char rx_byte_echo(void);
char rx_hex_echo(void);
int rx_hex_dbl_echo(void);
int rx_hex_word_echo(void);
void autobaud(void);
void putspace1(void);
void putcr(void);
Return SFR value pointed to by CADDR
(1)
Write to SFR pointed to by CADDR
(1)
Push registers and call cmd_parser
See SBAA076B.pdf
Output string
Erase flash page
Flash write
(2)
Write flash byte, verify
Write flash byte
(2)
Read HW config byte from faddr
Read xdata or code byte
Send byte to USART0
Send hex value to USART0
Send
“
x
”
to USART0 on R7 = 1
Read byte from USART0
Read and echo byte on USART0
Read and echo hex on USART0
Read int as hex and echo: USART0
Read int reversed as hex and echo: USART0
Set baud with received CR
(3)
Output 1 space to USART0
Output CR, LF to USART0
NOTES: (1) CADDR must be set using the faddr_data_read routine.
(2) MWS register (SFR 8F
) defines Data Memory or Program Memory write.
(3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00.
TABLE VI. MSC1200 Boot ROM Routines.
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