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參數(shù)資料
| 型號： | SC1200 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory |
| 中文描述： | 精密模擬到數(shù)字轉(zhuǎn)換器（ADC）和數(shù)字到模擬轉(zhuǎn)換器（DAC）的8051微控制器和閃存 |
| 文件頁數(shù)： | 18/60頁 |
| 文件大?。?/td> | 802K |
| 代理商： | SC1200 |
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MSC1200
SBAS289E
18
www.ti.com
FIGURE 8. Filter Step Responses.
SETTLING TIME
(Conversion Cycles)
FILTER
Sinc
3
Sinc
2
Fast
3
(1)
2
(1)
1
(1)
NOTE: (1) With Synchronized Channel Changes.
CONVERSION CYCLE
1
2
3
4+
Discard
Fast
Sinc
2
Sinc
3
AUTO MODE FILTER SELECTION
FILTER SETTLING TIME
Adjustable Digital Filter
Data Out
Modulator
Fast Settling
Sinc
2
Sinc
3
RMS
FULL-SCALE
RANGE
(V)
ENOB
AT 10Hz
(BITS)
MEASUREMENT
RESOLUTION
(nV)
PGA
SETTING
1
2
4
8
±
2.5
±
1.25
±
0.625
±
0.313
±
0.156
±
0.0781
±
0.039
±
0.019
21.7
21.5
21.4
21.2
20.8
20.4
20
19
1468
843
452
259
171
113
74.5
74.5
16
32
64
128
TABLE I. ENOB Versus PGA.
PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective resolution
of the ADC. For instance, with a PGA of 1 on a
±
2.5V full-
scale range, the ADC can resolve to 1.5
μ
V. With a PGA of
128 on a
±
19mV full-scale range, the ADC can resolve to
75nV. With a PGA of 1 on a
±
2.5V full-scale range, it would
require a 26-bit ADC to resolve 75nV, as shown in Table I.
OFFSET DAC
The analog output from the PGA can be offset by up to half
the full-scale input range of the PGA by using the ODAC
register (SFR E6
H
). The ODAC (Offset DAC) register is an 8-
bit value; the MSB is the sign and the seven LSBs provide
the magnitude of the offset. Since the ODAC introduces an
analog (instead of digital) offset to the PGA, using the ODAC
does not reduce the range of the ADC.
MODULATOR
The modulator is a single-loop 2nd-order system. The modu-
lator runs at a clock speed (f
MOD
) that is derived from the CLK
using the value in the Analog Clock register (ACLK, F6
H
).
The data output rate is:
Data Rate = f
DATA
=
f
DecimationRatio
MOD
where f
MOD
=
f
ACLK
f
CLK
+
ACLK
64
(
)
=
1
64
CALIBRATION
The offset and gain errors in the MSC1200, or the complete
system, can be reduced with calibration. Calibration is con-
trolled through the ADCON1 register (SFR DD
H
), bits
CAL2:CAL0. Each calibration process takes seven t
DATA
periods (data conversion time) to complete. Therefore, it
takes 14 t
DATA
periods to complete both an offset and gain
calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset calibration requires a
zero-differential input signal. It then computes an offset value
that will nullify offset in the system. The system gain calibration
requires a positive full-scale differential input signal. It then
computes a gain value to nullify gain errors in the system.
Each of these calibrations will take seven t
DATA
periods to
complete.
Calibration should be performed after power on, a change in
temperature, power supply, voltage reference, decimation
ratio, buffer, or a change of the PGA. Calibration will remove
the effects of the Offset DAC; therefore, changes to the
Offset DAC register should be done after calibration.
At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid data
is available.
DIGITAL FILTER
The Digital Filter can use either the Fast Settling, Sinc
2
, or
Sinc
3
filter, as shown in Figure 8. In addition, the Auto mode
changes the Sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
Fast Settling filter, for the next two conversions the first of
which should be discarded. It will then use the Sinc
2
followed
by the Sinc
3
filter to improve noise performance. This com-
bines the low-noise advantage of the Sinc
3
filter with the
quick response of the Fast Settling Time filter. The frequency
response of each filter is shown in Figure 9.
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