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參數(shù)資料
| 型號(hào)： | SC1200 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory |
| 中文描述： | 精密模擬到數(shù)字轉(zhuǎn)換器（ADC）和數(shù)字到模擬轉(zhuǎn)換器（DAC）的8051微控制器和閃存 |
| 文件頁數(shù)： | 27/60頁 |
| 文件大?。?/td> | 802K |
| 代理商： | SC1200 |
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MSC1200
SBAS289E
27
www.ti.com
Serial Flash Programming Mode
Two methods of programming are available: serial program-
ming mode and user application mode. Serial programming
mode is initiated by holding the P1.0/
PROG
pin low during
POR, as shown in Figure 21. User Application mode also
allows for Flash programming. Code execution from Flash
Memory cannot occur in this mode while programming, but
code execution can occur from Boot ROM while programming.
INTERRUPT
ENABLE
INTERRUPT/EVENT
ADDR
NUM
PRIORITY
FLAG
CONTROL
HIGH
0
0
0
0
0
0
0
1
2
3
4
5
AV
DD
Low Voltage Detect
Count (SPI/ I
2
C)
I
2
C Start/Stop
Milliseconds Timer
ADC
Summation Register
Seconds Timer
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port 0
33
H
33
H
33
H
33
H
33
H
33
H
33
H
03
H
0B
H
13
H
1B
H
23
H
6
6
6
6
6
6
6
0
1
2
3
4
ALVDIP (AIPOL.1)
(1)
CNTIP (AIPOL.2)
(1)
I2CIP (AIPOL.3)
(1)
MSECIP (AAIPOLIE.4)
(1)
ADCIP (AIPOL.5)
(1)
SUMIP (AIPOL.6)
(1)
SECIP (AIPOL.7)
(1)
IE0 (TCON.1)
(2)
TF0 (TCON.5)
(3)
IE1 (TCON.3)
(2)
TF1 (TCON.7)
(3)
RI_0 (SCON0.0)
TI_0 (SCON0.1)
IE2 (EXIF.4)
IE3 (EXIF.5)
IE4 (EXIF.6)
IE5 (EXIF.7)
WDTI (EICON.3)
EALV (AIE.1)
(1)
ECNT (AIE.2)
(1)
EI2C (AIE.3)
(1)
EMSEC (AIE.4)
(1)
EADC (AIE .5)
(1)
ESUM (AIE.6)
(1)
ESEC (AIE.7)
(1)
EX0 (IE.0)
(4)
ET0 (IE.1)
(4)
EX1 (IE.2)
(4)
ET1 (IE.3)
(4)
ES0 (IE.4)
(4)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
PS0 (IP.4)
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog
43
H
4B
H
53
H
5B
H
63
H
8
9
10
11
12
6
7
8
9
EX2 (EIE.0)
(4)
EX3 (EIE.1)
(4)
EX4 (EIE.2)
(4)
EX5 (EIE.3)
(4)
EWDI (EIE.4)
(4)
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
PWDI (EIP.4)
10
LOW
NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the
service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs.
(4) Globally enabled by EA (IE.7).
TABLE VII. Interrupt Summary.
INTERRUPT
INTERRUPTS
The MSC1200 uses a three-priority interrupt system. As
shown in Table VII, each interrupt source has an indepen-
dent priority bit, flag, interrupt vector, and enable (except that
nine interrupts share the Auxiliary Interrupt (AI) at the highest
priority). In addition, interrupts can be globally enabled or
disabled. The interrupt structure is compatible with the origi-
nal 8051 family. All of the standard interrupts are available.
HARDWARE CONFIGURATION MEMORY
The 64 configuration bytes can only be written during the
program mode. The bytes are accessed through SFR regis-
ters CADDR (SFR 93
H
) and CDATA (SFR 94
H
). Three of the
configuration bytes control Flash partitioning and system
control. If the security bit is set, these bits cannot be changed
except with a Mass Erase command that erases all of the
Flash Memory including the 64 configuration bytes.
FIGURE 21. Serial Programming Mode.
MSC1200
Programmer
P3.0/RxD0
P3.1/TxD0
P1.0/PROG
NOTE: For user application mode, avoid heavy loading on
P1.0/PROG, which may result in erroneously entering serial
programming mode on power-up.
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