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MSC1200
SBAS289E
34
www.ti.com
Timer Mode Control (TMOD)
7
6
5
4
3
2
1
0
TIMER 1
TIMER 0
Reset Value
SFR 89
H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00
H
GATE
bit 7
Timer 1 Gate Control.
This bit enables/disables the ability of Timer 1 to increment.
0: Timer 1 will clock when TR1 = 1, regardless of the state of pin
INT1
.
1: Timer 1 will clock only when TR1 = 1 and pin
INT1
= 1.
C/T
bit 6
Timer 1 Counter/Timer Select.
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88
H
) is 1.
M1, M0
bits 5-4
Timer 1 Mode Select.
These bits select the operating mode of Timer 1.
TL0.7-0
bits 7-0
Timer 0 LSB.
This register contains the least significant byte of Timer 0.
Timer 1 LSB (TL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8A
H
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
00
H
TL1.7-0
bits 7-0
Timer 1 LSB.
This register contains the least significant byte of Timer 1.
Timer 0 MSB (TH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8B
H
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
00
H
TH0.7-0
bits 7-0
Timer 0 MSB.
This register contains the most significant byte of Timer 0.
7
6
5
4
3
2
1
0
Reset Value
SFR 8C
H
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
00
H
GATE
bit 3
Timer 0 Gate Control.
This bit enables/disables the ability of Timer 0 to increment.
0: Timer 0 will clock when TR0 = 1, regardless of the state of pin
INT0
(software control).
1: Timer 0 will clock only when TR0 = 1 and pin
INT0
= 1 (hardware control).
C/T
bit 2
Timer 0 Counter/Timer Select.
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88
H
) is 1.
M1, M0
bits 1-0
Timer 0 Mode Select.
These bits select the operating mode of Timer 0.
M1
M0
MODE
0
0
1
1
0
1
0
1
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
Mode 2: 8-bit counter with auto reload.
Mode 3: Two 8-bit counters.
M1
M0
MODE
0
0
1
1
0
1
0
1
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
Mode 2: 8-bit counter with auto reload.
Mode 3: Two 8-bit counters.
Timer 0 LSB (TL0)