
SAB 82532/SAF 82532
Basic Functional Principles
Semiconductor Group
38
07.96
– Telecom specific features
In a special operating mode, the ESCC2 can transmit or receive data packets in one
of up to 64 time-slots of programmable width (clock mode 5). Furthermore, the ESCC2
can transmit or receive variable data portions within a defined window of one or more
clock cycles in conjunction with an external strobe signal (clock mode 1). These
features make the ESCC2 suitable for applications using time division multiplex
methods, such as time-slot oriented PCM systems or systems designed for packet
switching.
– FIFO buffers for efficient transfer of data packets
A further speciality of ESCC2 are the 64 byte deep FIFO buffers used for the
temporary storage of data packets transferred between the serial communications
interface and the parallel system bus. Because of the overlapping input/output
operation (dual-port behaviour), the maximum message length is not limited by the
size of the buffer. The dynamic load of the CPU is drastically reduced by transferring
the data packets block by block via Direct Memory Access supported by the ESCC2.
The CPU only has to initiate the data transmission by the ESCC2 and determine the
status in case of completed reception, but is not involved in data transfers.
– The 16-bit wide microprocessor interface enables high data throughput and offers a
high flexibility for connection to both 8/16-bit Siemens/Intel and Motorola type
microprocessor systems. Moreover, interrupt driven systems are supported by
vectorized interrupts and interrupt cascading capabilities.