
SAB 82532/SAF 82532
Detailed Register Description
Semiconductor Group
152
07.96
AOLP/ALLS …
Active On Loop
Only valid if SDLC Loop mode is selected.
It is set in response to a Go Active On Loop command, but not
before an EOP sequence has been received. TxD is disconnected
from RxD and transmission of flags or data is started.
All Sent
Only valid if SDLC loop mode is not selected.
This bit is set
– if the last bit of the current frame is completely sent out on TxD
and XFIFO is empty (non-auto mode, transparent modes),
– if an I-frame is completely sent out on TxD and a positive
acknowledgement has been received (auto mode),
– In auto-mode, if an I-frame has been sent and a timer interrupt
(TIN) is generated because the internal timer expires before an
acknowledgement is received: in this case ALLS is generated
one clock period after (TIN).
Transmit Data Underrun/Extended Transmission End
Transmitted frame was terminated with an abort sequence
because no data was available for transmission in XFIFO and no
XME was issued (interrupt mode) or DMA request was not
satisfied in time (DMA mode).
Note: Transmitter and XFIFO are reset and deactivated if this
condition occurs. They are reactivated not before this
interrupt status register has been read. Thus, XDU should
not be masked via register IMR1.
XDU/EXE …
In extended transparent mode, this bit indicates the
transmission-end condition (EXE).
Timer Interrupt
The internal timer and repeat counter has expired (see also
description of TIMR register).
TIN …
HDLC Mode