
SAB 82532/SAF 82532
Introduction
Semiconductor Group
12
07.96
11
43
RD/DS
I
Read Enable
(Siemens/Intel bus mode)
This signal indicates a read operation.
When the ESCC2 is selected via CS the
READ signal enables the bus drivers to
output data from an internal register
addressed via A0 … A6 on to Data Bus.
For more information about control/status
register and FIFO access in the different
bus interface modes refer to
chapter 2
.
If DMA transfer is selected via DACKA or
DACKB, the RD signal enables the bus
drivers to put data from the corresponding
Receive FIFO on the Data Bus. Inputs
A1 … A6 are ignored. A0 and BHE/BLE
are used to select byte or word access.
Data Strobe
(Motorola bus mode)
This pin serves as input to control
read/write operations.
12
44
WR/R/W
I
Write Enable
(Siemens/Intel bus mode)
This signal indicates a write operation.
When CS is active the ESCC2 loads an
internal register with data provided via the
Data Bus. For more information about
control/status register and FIFO access in
the different bus interface modes refer to
chapter 2
.
If DMA transfer is selected via DACKA or
DACKB, the WR signal enables latching
data from the Data Bus on the top of the
corresponding Transmit FIFO. Inputs
A0 … A6 are ignored.
Read/Write Enable
(Motorola bus mode)
This signal distinguishes between read
and write operation.
13
45
CS
I
Chip Select
A low signal selects the ESCC2 for
read/write operations. CS has no function
in interrupt acknowledge or DMA cycles.
1.3
Pin Definitions and Functions
(cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Function
P-LCC-68
P-MQFP-80