
SAB 82532/SAF 82532
BISYNC Mode
Detailed Register Description
Semiconductor Group
205
07.96
Command Register (CMDR)
Access: write
address: ch-A: 20
H
ch-B: 60
H
Value after RESET: 00
H
7
0
CMDR
RMC
RRES
RFRD
STI
XF
HUNT
XME
XRES
RMC …
Receive Message Complete
Confirmation from CPU to ESCC2 that the current frame or data
block has been fetched following an RPF or RME interrupt, thus
the occupied space in the RFIFO can be released.
Note: In DMA Mode, this command has to be issued after an
TCD interrupt in order to enable the generation of further
receiver DMA requests.
Receiver Reset
All data in RFIFO and receiver is deleted. The receiver returns to
Hunt state.
Receive FIFO Read Enable
The CPU can have access to RFIFO by issuing the RFRD
command before threshold level or the end condition (TCD) are
fulfilled. After issuing the RFRD command the CPU has to wait for
TCD interrupt, before reading RBC and RFIFO. The number of
valid
bytes
is determined by reading the RBCL register.
Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after
start.
Transmit Frame
Interrupt Mode
After having written up to 32 bytes/16 words to the XFIFO, this
command initiates the transmission of data.
DMA Mode
After having written the amount of data to be transmitted to the
XBCH, XBCL registers, this command initiates the data transfer
from system memory to ESCC2 by DMA. Serial data
transmission starts as soon as 32 bytes/16 words are stored in
the XFIFO or the Transmit Byte Counter value is reached.
RRES …
RFRD …
STI …
XF …