
SAB 82532/SAF 82532
BISYNC Mode
Detailed Register Description
Semiconductor Group
237
07.96
Channel Configuration Register 4 (CCR4)
(version 3 upwards, otherwise unused)
Access: read/write
address: ch-A: 3F
H
ch-B: 7F
H
Value after RESET: 00
H
Note: Unused bits have to be set to logical ‘0’.
7
0
CCR4
MCK4
EBRG
TST1
ICD
0
0
0
0
MCK4 …
Master Clock divide-by-4
This bit is valid when master clock option is selected by setting
CCR0:MCE = ‘1’.
0 … (default) XTAL 1-2 clock feeds the core logic and timer
blocks. This causes the XTAL frequency to be restricted to
10 MHz, thus limiting the highest baud rate to about
600 Kbit/s.
1 … XTAL 1-2 clock divide-by-4 feeds the core logic and timer
blocks. This allows the device to function with XTAL
frequency up to 30 MHz. The baud rate generator is fed
directly from the XTAL and can thus be used to provide
clocks for baud rates in excess of 2 Mbaud in asynch
oversampling mode. It also allows the timer block to operate
at the highest resolution.
Enhanced Baud Rate Generator Mode
0 … (default) selects standard baud rate generator operation.
See description of BRG register.
1 … selects enhanced baud rate generator. See description of
BRG register.
Test Pin
Write ‘0’ for normal operation.
Invert Polarity of Carrier Detect Signal
0 … (default)
selects
the
current
Detect CD (active ‘HIGH’)
1 … selects the invert polarity to be more consistent with other
equipment, Carrier Detect/CD (Active ‘LOW’).
As CD is a multifunctional pin, the ICD bit may only be set if CD
functionality is being used.
EBRG …
TST1 …
ICD …
polarity
for
Carrier