
SAB 82532/SAF 82532
Detailed Register Description
Semiconductor Group
135
07.96
Channel Configuration Register 1 (CCR1)
Access: read/write
address: ch-A: 2D
H
ch-B: 6D
H
Value after RESET: 00
H
7
0
CCR1
SFLG
GALP
GLP
ODS
ITF/
OIN
CM2
CM1
CM0
SFLG …
Enable Shared Flags
If this bit is set, the closing FLAG of a preceding frame
simultaneously becomes the opening FLAG of the following
frame.
Go Active On Loop
Only used if SDLC Loop is enabled.
This bit enables transmission on an SDLC Loop.
1 … After detection of the next EOP sequence, the ESCC2 goes
to the Sending On Loop state by changing the seventh ‘1’-bit
of the EOP sequence into a ‘0’, thus creating a Start Flag,
and by disconnecting the TxD pin from the RxD pin. The
ESCC2 is now active on loop and can transmit frames as
soon as data is available in the XFIFO. The time between
frames is always filled by sending continuous Flags
(independent from the value of bit CCR1:ITF), thus
occupying the loop.
0 … The ESCC2 leaves the Sending On Loop state when the
XFIFO is empty by retransmitting data received on RxD to
TxD (with one bit delay) after the closing flag has been
transmitted (thus creating an EOP sequence).
Go On Loop
Only used if SDLC Loop is enabled.
This command controls entering and leaving the SDLC Loop.
1 … The ESCC2 enters the On Loop state after detection of the
next EOP sequence by adding a ‘1’-bit delay between
receive and transmit path. The On Loop state is prerequisite
for sending frames on loop.
0 … The ESCC2 leaves the On Loop state by suppressing the
‘1’-bit delay after detection of the next EOP sequence.
GALP …
GLP …
HDLC Mode