
SAB 82532/SAF 82532
BISYNC Mode
Detailed Register Description
Semiconductor Group
232
07.96
Interrupt Mask Register 0, 1 (IMR0, IMR1)
Access: write
address: ch-A: 3A
H
(IMR0), 3B
H
(IMR1)
ch-B: 7A
H
(IMR0), 7B
H
(IMR1)
Value after RESET: FF
H
, FF
H
Note: Unused bits have to be set to logical ‘1’.
Each interrupt source can generate an interrupt signal at port INT (function of the output
stage is defined via register IPC). A ‘1’ in a bit position of IMR0 or IMR1 sets the mask
active for the interrupt status in ISR0 or ISR1. Masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are they visible in register GIS.
Moreover, they will
– not be displayed in the Interrupt Status Register if bit IPC:VIS is set to ‘0’
– be displayed in the Interrupt Status Register if bit IPC:VIS is set to ‘1’
Note: After RESET, all interrupts are
dis
abled.
TIN …
Timer Interrupt
The internal timer has expired (see also description of TIMR
register).
Clear To Send Status Change
Indicates that a state transition has occurred on CTS. The actual
state of CTS can be read from STAR register (CTS bit).
Transmit Message Repeat
The transmission of the last block of characters has to be
repeated because
– a collision occurred while transmitting a character in a bus
configuration, or
– CTS (transmission enable) has been withdrawn during
transmission of a character in point-to-point configuration.
Transmit Pool Ready
A data block of up to 32 bytes can be written to XFIFO.
CSC …
XMR …
XPR …
7
0
IMR0
TCD
1
PERR
SCD
PLLA
CDSC
RFO
RPF
IMR1
1
1
ALLS
XDU
TIN
CSC
XMR
XPR