
SAB 82532/SAF 82532
Introduction
Semiconductor Group
29
07.96
Another significant advantage of the ADMA is its Data Chaining feature, providing an
optimized memory management for receive and transmit data. Recording the ESCC2, a
linked chain of 32 byte deep buffers can be set up, which are subsequently filled with the
contents of the ESCC2’s FIFOS during reception. Unused buffers can be saved and
linked to another buffer chain reserved for the reception of the next frame.
As a result, it is not necessary to reserve a very large space in system memory, for
example determined by the maximum frame length of every received frame.
In this example, the ADMA works directly on the CPU’s local bus and shares the same
bus interface logic (Address Latches, Transceivers, Bus Controller) with the 80286.
Since one DMA Acknowledge line is provided for each DMA Request, two DACKn
outputs must be ‘AND’ed together for input to the ESCC2.
The ESCC2’s data lines (D0 … D15) are connected to the system data bus and the
address lines to A0 … A6. Pin WIDTH has to be tied to
V
DD
to select the 16-bit interface
mode of the ESCC2, pin ALE has to be fixed to
V
SS
to enable demultiplexed Intel bus
interface.
1.6.2.4 ESCC2 with 80386 or SAB-R3000 (MIPS)
In high-performance 32-bit systems based on 80386 or SAB-R3000 microprocessors a
separate control logic (e.g. sequencer PALs) is normally provided to generate all
necessary control signals for interfacing to I/O devices. Address and data lines are
buffered via latches or transceivers.