
SAB 82532/SAF 82532
Detailed Register Description
Semiconductor Group
151
07.96
Interrupt Status Register 1 (ISR1)
Access: read
address: ch-A: 3B
H
ch-B: 7B
H
Value after RESET: 00
H
All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding
interrupt vector is output.
Note: If bit IPC:VIS is set to ‘1’, interrupt statuses in ISR1 may be flagged although they
are masked via register IMR1. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
7
0
ISR1
EOP
OLP/
RDO
AOLP/
ALLS
XDU/
EXE
TIN
CSC
XMR
XPR
EOP …
End of Poll Sequence Detected
Only valid if SDLC Loop mode is selected.
It is set if an EOP sequence has been received.
On Loop
Only valid if SDLC Loop mode is selected.
It is set in response to a Go On Loop command, but not before an
EOP sequence has been received. It is also set when returning
from the Active On Loop state. All incoming bits on RxD are
reflected onto TxD with one bit delay.
OLP/RDO …
Receive Data Overflow
Not applicable in SDLC Loop mode
This interrupt status is an early warning that data has been lost. It
is classified as group 7 or group 8 interrupt. Even when this
interrupt status is generated, the frame continues to be received
when space in the RFIFO is available again.
Note: Whereas the bit RSTA:RDO in the frame status byte
indicates whether an overflow occurred when receiving the
frame currently accessed in the RFIFO, the ISR1:RDO
interrupt status is generated as soon as an overflow occurs
and does not necessarily pertain to the frame currently
accessed by the processor or the DMA controller.
HDLC Mode