
SAB 82532/SAF 82532
BISYNC Mode
Detailed Register Description
Semiconductor Group
222
07.96
Channel Configuration Register 3 (CCR3)
Access: read/write
address: ch-A: 2F
H
ch-B: 6F
H
Value after RESET: 00
H
7
0
CCR3
PRE1
PRE0
EPT
CON
CRL
CAPP
CRCM
PSD
PRE1 … PRE0 …
Number of Preamble Repetition
If preamble transmission is enabled, the preamble defined via
register PRE is transmitted
00 … 1 times
01 … 2 times
10 … 4 times
11 … 8 times.
Enable Preamble Transmission
This bit enables transmission of a preamble. The preamble is
started after Interframe Time Fill transmission has been stopped
and a new block of data is about to be transmitted. The preamble
consists of an 8-bit pattern defined via register PRE which is
repeated a number of times selected by bits PRE0 and PRE1.
CRC ON
This bit determines whether the current data written to XFIFO has
to be included into CRC calculation or not. It has to be
programmed
before
the assigned byte/word is written to XFIFO.
In the case of word access,
both
characters are included. Since
this control bit is copied in the XFIFO every time a character is
written, it is not necessary to reprogram it for each character when
consecutive characters are to be either all included into or all
excluded from CRC calculation.
0 … data not included
1 … data included.
CRC Reset Level
This bit defines the initialization for internal transmit CRC
generator.
0 … Initialized to ‘FFFF
H
’.
1 … Initialized to ‘0000
H
’.
Note: The internal transmit CRC generator is automatically
initialized before transmission of a new frame starts.
EPT …
CON …
CRL …