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參數(shù)資料
| 型號(hào)： | S71WS512NC0BFWY63 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁(yè)數(shù)： | 29/188頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BFWY63 |
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September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
27
A d v a n c e I n f o r m a t i o n
10.3
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections
10.3.4
and
10.3.5
, and
10.3.6
.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (t
IACC
) of each burst
access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See
Section
10.3.7
,
Configuration Register
, and
Table 15.1
,
Memory Array Commands
for further details.
Figure 10.1 Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
t
IACC
specification: the time from the rising edge of the first clock cycle after addresses are
latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that t
IACC
is
lengthened.
The device outputs subsequent words t
BACC
after the active edge of each successive clock cycle,
which also increments the internal address counter. The device outputs burst data at this rate sub-
ject to the following operational conditions:
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
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相關(guān)代理商/技術(shù)參數(shù) |
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| S71WS512NC0BFWY70 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY72 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY73 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWYJ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWYJ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
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