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參數(shù)資料
| 型號(hào)： | S71WS512NC0BFWY63 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP） |
| 文件頁(yè)數(shù)： | 110/188頁(yè) |
| 文件大?。?/td> | 2252K |
| 代理商： | S71WS512NC0BFWY63 |
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108
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
A d v a n c e I n f o r m a t i o n
Note:
The address bits other than those listed in the table above are reserved. For example, Burst Length address
bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then
the mode will be set to the default mode. Each field has its own default mode as indicated. A12 is a reserved bit for future
use. A12 must be set as
0
. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion.
The 256 word Full page burst mode needs to meet t
(Burst Cycle time) parameter as max. 2500 ns.
The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, implement
at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode.
The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the
transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
22.2
Mode Register Setting Timing
In this device, the MRS# pin is used for two purposes. One is to get into the mode register setting
and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting,
the system must drive MRS# pin to V
IL
and immediately (within 0.5μs) issue a write command
(drive CS#, ADV#, UB#, LB# and WE# to V
IL
and drive OE# to V
IH
during valid address). If the
subsequent write command (WE# signal input) is not issued within 0.5μs, then the device might
get into the PAR mode. This device supports software access control type mode register setting
timing. This timing consists of 5 cycles of Read operation. Each cycle of Read Operation is normal
asynchronous read operation. Clock and ADV# are don’t care and WAIT# signal is High-Z. CS#
should be toggling between cycles. The address for 1st, 2nd and 3rd cycle should be 3FFFFF(h)
and the address for 4th cycle should be 3FFEFF. The address for 5th cycle should be MRS code
(Register setting values).
Figure 22.1 Pin MRS Timing Waveform (OE# = V
IH
)
Partial Array Refresh
PAR Array
PAR Size
A4
1
1
A3
0
1
PAR
A2
0
1
PARA
A1
0
0
1
1
A0
0
1
0
1
PARS
PAR Enable
PAR Disable (default)
Bottom Array (default)
Top Array
Full Array (default)
3/4 Array
1/2 Array
1/4 Array
t
WU
Address
WE#
t
WC
t
CW
t
AW
t
BW
t
WP
t
AS
t
MW
CS#
ADV#
MRS#
UB#, LB#
Register Write Start
Register Write Complete
Register Update Complete
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512NC0BFWY70 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY72 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWY73 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWYJ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BFWYJ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
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