參數(shù)資料
型號(hào): S71PL129JA0BFI9P2
廠商: SPANSION LLC
元件分類(lèi): 存儲(chǔ)器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA64
封裝: 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64
文件頁(yè)數(shù): 87/149頁(yè)
文件大?。?/td> 2693K
代理商: S71PL129JA0BFI9P2
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Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
87
A d v a n c e I n f o r m a t i o n
Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than t
RC
min. sustain over 10 μs
in an active status, at least one valid address cycle over t
RC
min. is required dur-
ing 10μs.
W rite
In case multiple invalid address cycles shorter than t
WC
min. sustain over 10 μs
in an active status, at least one valid address cycle over t
WC
min. is required dur-
ing 10 μs.
Notes:
1.
Stresses greater than listed under "
Absolute Maximum Ratings
" section may cause permanent damage to the device.
2.
All voltages are reference to GND.
3.
I
DDO
depends on the cycle time.
4.
I
DDO
depends on output loading. Specified values are defined with the output open condition.
5.
AC measurements are assumed t
R
, t
F
= 5 ns.
6.
Parameters t
OD
, t
ODO
, t
BD
and t
OD
W define the time at which the output goes the open condition and are not output voltage
reference levels.
7.
Data cannot be retained at deep power-down stand-by mode.
8.
If OE# is high during the write cycle, the outputs will remain at high impedance.
9.
During the output state of I/O signals, input signals of reverse polarity must not be applied.
10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
Figure 30. Read
Figure 31. Write
over 10
μ
s
t
RC
min
CE1#
WE#
Address
t
WP
min
t
WC
min
CE1#
WE#
Address
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