- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄365444 > S71PL129JA0BFI9P2 (SPANSION LLC) Stacked Multi-Chip Product (MCP) Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | S71PL129JA0BFI9P2 |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64 |
| 文件頁(yè)數(shù)： | 56/149頁(yè) |
| 文件大?。?/td> | 2693K |
| 代理商： | S71PL129JA0BFI9P2 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)
56
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1.
See
Table 1
for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are write operations.
4.
During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5.
The reset command returns device to reading array.
6.
Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =
0 in cycle 6, program command must be issued and verified again.
7.
Data is latched on the rising edge of WE#.
8.
Entire command sequence must be entered for each portion of password.
9.
Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 μs timeout is required between any two portions of password.
12. A 100 μs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase
command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determine the status of a program or erase opera-
tion: DQ2, DQ3, DQ5, DQ6, and DQ7.
Table 14
and the following subsections describe
the function of these bits. DQ7 and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-
gram or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement
of the datum programmed to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is complete, the device out-
puts the datum programmed to DQ7. The system must provide the program address
to read valid status information on DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately 1 μs, then that bank returns
to the read mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL129JC0BFW9Z0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BFW9Z0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFW9Z0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JC0BAW9Z2 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BAW9Z2 | Stacked Multi-Chip Product (MCP) Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL129JA0BFI9P3 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9U0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9U2 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9U3 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9Z0 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。