參數(shù)資料
型號： S71PL129JA0BFI9P2
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA64
封裝： 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64
文件頁數(shù)： 20/149頁
文件大?。?/td> 2693K
代理商： S71PL129JA0BFI9P2
20
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Random Read ( Non-Page Read)
Address access time (t
ACC
) is equal to the delay from stable addresses to valid
output data. The chip enable access time (t
CE
) is the delay from the stable ad-
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least t
ACC
–t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t
ACC
or t
CE
and subsequent page read ac-
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t
PACC
. When CE1# and CE#2 are deasserted (= V
IH
), the
reassertion of CE1# or CE#2 for subsequent access has access time of t
ACC
or
t
CE
. Here again, CE1#/CE#2 selects the device and OE# is the output control and
should be used to gate data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping Amax–A3 constant and changing
A2–A0 to select the specific word within that page.
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be selected by bank addresses
(A21–A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
Table 2.
Page Select
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Bank
CE1#
CE2#
PL129J: A21–A20
Bank 1A
0
1
00
Bank 1B
0
1
01, 10, 11
相關PDF資料
PDF描述
S71PL129JC0BFW9Z0 Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JB0BFW9Z0 Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JA0BFW9Z0 Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JC0BAW9Z2 Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JB0BAW9Z2 Stacked Multi-Chip Product (MCP) Flash Memory
相關代理商/技術參數(shù)
參數(shù)描述
S71PL129JA0BFI9P3 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JA0BFI9U0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JA0BFI9U2 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JA0BFI9U3 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory
S71PL129JA0BFI9Z0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory
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