- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365444 > S71PL129JA0BFI9P2 (SPANSION LLC) Stacked Multi-Chip Product (MCP) Flash Memory PDF資料下載
參數(shù)資料
| 型號： | S71PL129JA0BFI9P2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 48/149頁 |
| 文件大小： | 2693K |
| 代理商： | S71PL129JA0BFI9P2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當(dāng)前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁
48
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does
not
require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.
Table 12
shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
“Write Op-
eration Status”
on page 56 for information on these status bits.
Any commands written during the chip erase operation are ignored.
Note that Se-
cured Silicon Sector, autoselect, and CFI functions are unavailable when a
[program/erase] operation is in progress.
However, note that a
hardw are reset
immediately terminates the erase operation. If that occurs, the chip erase com-
mand sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5
illustrates the algorithm for the erase operation. See the
Erase/Program
Operations
tables in
AC Characteristics
for parameters, and
Figure 16
for timing
diagrams.
Note:
See
Table 12
for program command sequence.
Figure 4. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL129JC0BFW9Z0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BFW9Z0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFW9Z0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JC0BAW9Z2 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BAW9Z2 | Stacked Multi-Chip Product (MCP) Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL129JA0BFI9P3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9U0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9U2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9U3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JA0BFI9Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。