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參數(shù)資料
| 型號： | S5935QF |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 19/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935QF |
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2-11
SIGNAL DESCRIPTIONS
S5935
Signal
Type
Description
System Pins — PCI Local Bus
Signal
Type
Description
Interface Control Pins — PCI Bus Signal
CLK
in
Clock. The rising edge of this signal is the reference upon which all other signals are
based, with the exception of RST# and the interrupt (IRQA#-). The maximum fre-
quency for this signal is 33 MHz and the minimum is DC (0 Hz).
RST#
in
Reset. This signal is used to bring all other signals within this device to a known,
consistent state. All PCI bus interface output signals are not driven (tri-stated), and
open drain signals such as SERR# are floated.
FRAME#
s/t/s
Frame. This signal is driven by the current bus master and identifies both the begin-
ning and duration of a bus operation. When FRAME# is first asserted, it indicates that
a bus transaction is beginning and that valid addresses and a corresponding bus
command are present on the AD[31:00] and C/BE[3:0] lines. FRAME# remains as-
serted during the data transfer portion of a bus operation and is deasserted to signify
the final data phase.
IRDY#
s/t/s
Initiator Ready. This signal is sourced by the bus master and indicates that the bus
master is able to complete the current data phase of a bus transaction. For write
operations, it indicates that valid data is on the AD[31:00] pins. Wait states occur until
both TRDY# and IRDY# are asserted together.
TRDY#
s/t/s
Target Ready. This signal is sourced by the selected target and indicates that the
target is able to complete the current data phase of a bus transaction. For read
operations, it indicates that the target is providing valid data on the AD[31:00] pins.
Wait states occur until both TRDY# and IRDY# are asserted together.
STOP#
s/t/s
Stop. The Stop signal is sourced by the selected target and conveys a request to the
bus master to stop the current transaction.
LOCK#
in
Lock. The lock signal provides for the exclusive use of a resource. The S5935 may
be locked as a target by one master at a time. The S5935 cannot lock a target when
it is a master.
IDSEL
in
Initialization Device Select. This pin is used as a chip select during configuration read
or write operations.
DEVSEL#
s/t/s
Device Select. This signal is sourced by an active target upon decoding that its
address and bus commands are valid. For bus masters, it indicates whether any
device has decoded the current bus cycle.
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| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
| S5629 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
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