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參數(shù)資料
| 型號(hào)： | S5935QF |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 134/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935QF |
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10-126
FIFO OVERVIEW
S5935
Figure 7 shows a synchronous FIFO register burst
access. SELECT# must meet setup and hold times
relative to the rising edge of BPCLK. RD# and
SELECT# both asserted enables the DQ outputs, and
the first data location (data 0) in the FIFO is driven on
to the bus. The FIFO address and the byte enables
must be valid before valid data is driven onto the DQ
bus. Data 0 remains valid until the next rising edge of
BPCLK. The rising edge of BPCLK causes the FIFO
pointer to advance to the next location (data 1). The
next rising edge of BPCLK also advances the FIFO
pointer to the next location (data 2). The status outputs
reflect the FIFO condition after it advances, and are
updated off of the rising edge of BPCLK. When RD# or
SELECT# is deasserted, the DQ bus floats. The next
time a valid FIFO access occurs and RD# and SELECT#
are asserted, data 2 is presented on the DQ bus (as
there was no BPCLK edge to advance the FIFO).
Add-On FIFO Direct Access Mode
Instead of generating an address, byte enables, SELECT#
and a RD# or WR# strobe for every FIFO access, the
S5935 allows a simple, direct access mode. Using
RDFIFO# and WRFIFO# is functionally identical to per-
forming a standard AFIFO Port Register access, but re-
quires less logic to implement. Accesses to the FIFO
register using the direct access signals are always 32-
bits wide. The only exception to this is when the
MODE pin is configured for 16-bit operation. In this
situation, all accesses are 16-bits wide. The RD# and
WR# inputs must be inactive when RDFIFO# or
WRFIFO# is active. The ADR[6:2] and BE[3:0]# inputs
are ignored.
RDFIFO# and WRFIFO# act as enables with BPCLK
acting as the clock. A Synchronous interface allows
higher data rates.
Figure 8 shows a synchronous FIFO register direct
burst access using RDFIFO#. RDFIFO# acts as an
enable and the first data location (data 0) in the FIFO
is driven on to the bus when RDFIFO# is asserted.
Data 0 remains valid until the next rising edge of
BPCLK. The rising edge of BPCLK causes the FIFO
pointer to advance to the next location (data 1). The
next rising edge of BPCLK advances the FIFO
pointer to the next location (data 2). The status out-
puts reflect the FIFO condition after it advances, and
are updated off of the rising edge of BPCLK. When
RDFIFO# is deasserted, the DQ bus floats. The next
time RDFIFO# is asserted, data 2 is presented on the
DQ bus (as there was no BPCLK edge to advance
the FIFO).
A synchronous FIFO interface has the advantage of
allowing data to be accessed more quickly (in bursts)
by the Add-On. As a target, if a full S5935 FIFO is
written (or an empty FIFO is read) by a PCI initiator,
the S5935 requests a retry. The faster the Add-On
interface can empty (or fill) the FIFO, the less often
retries occur. With the S5935 as a PCI initiator, a
similar situation occurs. Not emptying or filling the
FIFO quickly enough results in the S5935 giving up
control of the PCI bus. Higher PCI bus data transfer
rates are possible through the FIFO with a synchro-
nous interface.
Figure 7. Synchronous FIFO Register Burst Read Access Example
BE[3:0]#
BPCLK
ADR[6:2]
DQ[31:0]
SELECT#
RD#
RDEMPTY
Valid Byte Enables
FIFO Pointer Advances
Valid Address
Data 1
Data 2
Data 0
New Status
New Status
Status Before Read
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相關(guān)代理商/技術(shù)參數(shù) |
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| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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