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參數資料
| 型號： | S5935QF |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 111/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935QF |
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8-103
ADD-ON BUS INTERFACE
S5935
Mailbox Interrupts
Mailboxes can be configured to generate Add-On in-
terrupts (IRQ#) and/or allow the Add-On to generate
PCI interrupts (INTA#). Mailbox empty/full status con-
ditions be can used to interrupt the Add-On or PCI
host to indicate some action is required. An individual
mailbox byte is selected to generate an interrupt
when accessed. An outgoing mailbox becoming
empty or an incoming mailbox becoming full asserts
the interrupt output (if enabled).
When used with a serial nv memory boot device, the
mailboxes also provide a way to generate PCI inter-
rupts (INTA#) through hardware. When a serial nv
memory boot device is used, the device pin functions
EA0 - EA8 are redefined. These pins then provide
direct, external access to the Add-On outgoing mail-
box 4, byte 3 (which is also PCI incoming mailbox 4,
byte 3).
FIFO BUS INTERFACE
The FIFO register on the Add-On interface may only
be accessed synchronously or asynchronously. Lo-
cation 45h, bits 6 and 5 in the nv memory boot device
must be programmed to a “0” for correct operation.
FIFO Direct Access Inputs
RDFIFO# and WRFIFO# are referred to as FIFO ‘di-
rect access’ inputs. Asserting RDFIFO# is function-
ally identical to accessing the FIFO with RD#,
SELECT#, BE[3:0]#, and ADR[6:2]. Asserting
WRFIFO# is functionally identical to accessing the
FIFO with WR#, SELECT#, BE[3:0]#, and ADR[6:2].
RD# and WR# must be deasserted when RDFIFO#
or WRFIFO# is asserted, but SELECT# may be as-
serted. These inputs automatically drive the address
(internally) to 20h and assert all byte enables. The
ADR[6:2] and BE[3:0]# inputs are ignored when us-
ing the FIFO direct access inputs. RDFIFO# and
WRFIFO# are useful for Add-On designs which cas-
cade an external FIFO into the S5935 FIFO or use
dedicated external logic to access the FIFO.
Direct access signals always access the FIFO as 16-
bits or 32-bits, whatever the MODE pin is configured
for. For 16-bit mode, two consecutive accesses fill or
empty the 32-bit FIFO register.
FIFO Status Signals
The FIFO Status signals indicate to the Add-On logic
the current state of the S5935 FIFO. A FIFO status
change caused by a PCI FIFO access is reflected
one PCI clock period after the PCI access is com-
pleted (TRDY# asserted). A FIFO status change
caused by an Add-On FIFO access is reflected im-
mediately (after a short propagation delay) after the
access occurs. For Add-On accesses, FIFO status is
updated after the rising edge of BPCLK for synchro-
nous interfaces or after the rising edge of the read or
write strobe for asynchronous interfaces.
FIFO Control Signals
For Add-On initiated PCI bus mastering, the FIFO
status reset controls FWC# (Add-On to PCI FIFO
clear) and FRC# (PCI to Add-On FIFO clear) are
available. FWC# and FRC# must be asserted for a
minimum of one BPCLK period to be recognized.
These inputs are sampled at the rising edge of BPCLK.
These inputs should not be asserted unless the FIFO is
idle. Asserting a FIFO status reset input during a PCI or
Add-On FIFO access results in indeterminate operation.
For Add-On initiated bus master transfers, AMREN
(Add-On bus master read enable) and AMWEN (Add-
On bus master write enable) are used, in conjunction
with the appropriate FIFO status signals, to enable
the S5935 to assert its PCI bus request (REQ#).
PASS-THRU BUS INTERFACE
The S5935 Pass-Thru interface is synchronous. The
Add-On Pass-Thru Address (APTA) and Add-On
Pass-Thru Data (APTD) registers may be accessed
pseudo-synchronously.
Although BPCLK is used to clock data into and out of
the Pass-Thru registers, accesses may be performed
asynchronously. For reads, APTA or APTD data re-
mains valid as long as RD# (or PTADR#) is asserted.
A new value is not driven until PTRDY# is asserted
by Add-On logic. For writes to APTD, data is clocked
into the S5935 on every BPCLK rising edge, but is
not passed to the PCI bus until PTRDY# is asserted.
PTRDY# must by synchronized to BPCLK.
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相關代理商/技術參數 |
參數描述 |
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| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
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