參數(shù)資料
型號: S29NS032JPLBJW000
廠商: Spansion Inc.
英文描述: 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述: 110納米CMOS 1.8伏只有同時讀/寫,突發(fā)模式閃存
文件頁數(shù): 72/85頁
文件大小: 799K
代理商: S29NS032JPLBJW000
68
S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
Erase and Programming Performance
Notes:
1.
assume checkerboard pattern.
2.
Under worst case conditions of 90°C, V
CC
= 1.7 V, 1,000,000 cycles.
3.
The typical chip programming time is considerably less than the maximum chip programming time listed.
4.
In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5.
System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 18
for
further information on command definitions.
6.
The device has a minimum erase and program cycle endurance of 100,000 cycles.
Typical program and erase times assume the following conditions: 25
°
C, 1.8 V V
CC
, 100,000 cycles. Additionally, programming typicals
BGA Ball Capacitance
Notes:
1.
Sampled, not 100% tested.
2.
Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
Typ
(
Note 1
)
Max
(
Note 2
)
Unit
Comments
Sector Erase Time
32 Kword
0.4
5
s
Excludes 00h programming
prior to erasure (
Note 4
)
8 Kword
0.2
5
Chip Erase Time
128 Mb
108
s
64 Mb
54
32 Mb
27
16 Mb
13.5
Word Programming Time
9
210
μs
Excludes system level
overhead (
Note 5
)
Accelerated Word Programming Time
4
120
μs
Chip Programming Time (
Note 3
)
128 Mb
96
288
s
Excludes system level
overhead (
Note 5
)
64 Mb
48
144
32 Mb
24
72
16 Mb
12
36
Accelerated Chip Programming Time
128 Mb
32
96
s
64 Mb
16
48
32 Mb
8
24
16 Mb
4
12
Accelerated Chip Erase Time
128 Mb
50
s
64 Mb
25
32 Mb
12.5
16 Mb
6.25
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
4.2
5.0
pF
C
OUT
Output Capacitance
V
OUT
= 0
5.4
6.5
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
3.9
4.7
pF
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