參數(shù)資料
型號： S29NS032JPLBJW000
廠商： Spansion Inc.
英文描述： 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述： 110納米CMOS 1.8伏只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 41/85頁
文件大?。?/td> 799K
代理商： S29NS032JPLBJW000
March 22, 2006 S29NS-J_00_A10
S29NS-J
37
D a t a S h e e t
Programming is allowed in any sequence and across sector boundaries.
A bit cannot be pro-
grammed from “ 0” back to a “ 1.”
Attempting to do so may cause that bank to set DQ5 = 1,
or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a suc-
ceeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Note: By default, upon every power up, the sectors will automatically be locked.
Therefore, everytime after power-up, users need to write unlock command to unlock the sectors
before giving program/erase command.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program to a bank faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle containing the unlock bypass command,
20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in this sequence
contains the unlock bypass program command, A0h; the second cycle contains the program ad-
dress and data. Additional data is programmed in the same manner. This mode dispenses with
the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time.
Table 18
shows the requirements for the unlock bypass command
sequences.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.
The device offers accelerated program operations through the A
cc
input. When the system asserts
A
cc
on this input, the device automatically enters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command sequence. The device uses the higher volt-
age on the A
cc
input to accelerate the operation.
Figure 1
illustrates the algorithm for the program operation. Refer to the
Erase/Program Opera-
tions
table in the AC Characteristics section for parameters, and
Figure 15
for timing diagrams.
相關PDF資料
PDF描述
S29NS032JPLBJW002 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
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相關代理商/技術參數(shù)
參數(shù)描述
S29NS032JPLBJW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032JPLBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS064J0LBAW00 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS064J0LBAW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories
S29NS064J0LBAW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories
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