參數(shù)資料
型號(hào): S29NS032JPLBJW000
廠商: Spansion Inc.
英文描述: 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述: 110納米CMOS 1.8伏只有同時(shí)讀/寫,突發(fā)模式閃存
文件頁數(shù): 60/85頁
文件大?。?/td> 799K
代理商: S29NS032JPLBJW000
56
S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
AC Characteristics
Synchronous/Burst Read
Note: Not 100% tested
Notes:
1.
Figure shows total number of clock set to five.
2.
If any burst address occurs at a 64-word boundary, two additional clock cycles are inserted and are indicated by RDY.
Figure 11. Burst Mode Read (66 and 54 MHz)
Parameter
Description
0P
(66 MHz)
0L
(54 MHz)
Unit
J EDEC
Standard
t
IACC
Initial Access Time
Max
71
87.5
ns
t
BACC
Burst Access Time Valid Clock to Output Delay
Max
11
13.5
ns
t
AVDS
AVD# Setup Time to CLK
Min
4
5
ns
t
AVDH
AVD# Hold Time from CLK
Min
6
7
ns
t
AVDO
AVD# High to OE# Low
Min
0
ns
t
ACS
Address Setup Time to CLK
Min
4
5
ns
t
ACH
Address Hold Time from CLK
Min
6
7
ns
t
BDH
Data Hold Time from Next Clock Cycle (Note)
Min
3
ns
t
OE
Output Enable to Data, PS, or RDY Valid
Max
11
13.5
ns
t
CEZ
Chip Enable to High Z
Max
10
ns
t
OEZ
Output Enable to High Z
Max
10
ns
t
CES
CE# Setup Time to CLK
Min
4
5
ns
t
RDYS
RDY Setup Time to CLK
Min
4
5
ns
t
RACC
Ready access time from CLK
Max
11
13.5
ns
Da
Da + 1
Da + 2
Da + n
OE#
A/DQ15
A/DQ0
Amax
A16
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVDH
t
AVDO
t
ACH
t
BACC
t
RACC
t
OE
t
OEZ
t
CEZ
t
IACC
t
RYDS
t
BDH
Aa
Progra5 cycles for initial access shown.
15.2 ns typ. (66 MHz)
Hi-Z
Hi-Z
Hi-Z
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