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參數(shù)資料
| 型號(hào)： | S29NS032JPLBJW000 |
| 廠商： | Spansion Inc. |
| 英文描述： | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| 中文描述： | 110納米CMOS 1.8伏只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 18/85頁 |
| 文件大小： | 799K |
| 代理商： | S29NS032JPLBJW000 |
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14
S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device.
Table 1
lists the device bus operations, the inputs and control levels they require, and
the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Device Bus Operations
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care.
Requirements for Asynchronous Read Operation (Non-Burst)
To read data from the memory array, the system must assert a valid address on A/DQ15–A/DQ0
and A
max
–A16, while AVD# and CE# are at V
IL
. WE# should remain at V
IH
. Note that CLK must
remain at V
IL
during asynchronous read operations. The rising edge of AVD# latches the address,
after which the system can drive OE# to V
IL
. The data will appear on A/DQ15–A/DQ0. (See
Figure
13
.) Since the memory array is divided into four banks, each bank remains enabled for read ac-
cess until the command register contents are altered.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The
chip enable access time (t
CE
) is the delay from the stable addresses and stable CE# to valid data
at the outputs. The output enable access time (t
OE
) is the delay from the falling edge of OE# to
valid data at the output.
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition.
Requirements for Synchronous (Burst) Read Operation
The device is capable of seven different burst read modes (see
Table 11
): continuous burst read;
8-, 16-, and 32-word linear burst reads with wrap around; and 8-, 16-, and 32-word linear burst
reads without wrap around.
Operation
CE#
OE#
WE#
A
max
–16
Addr In
A/DQ15–0
RESET#
CLK
AVD#
Asynchronous Read
L
L
H
I/O
H
L
Write
L
H
L
Addr In
I/O
H
H/L
Standby (CE#)
H
X
X
X
HIGH Z
H
H/L
X
Hardware Reset
X
X
X
X
HIGH Z
L
X
X
Burst Read Operations
Load Starting Burst Address
L
H
H
Addr In
Addr In
H
Advance Burst to next address with
appropriate Data presented on the Data Bus
L
L
H
X
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
X
HIGH Z
H
X
Terminate current Burst read cycle via
RESET#
X
X
H
X
HIGH Z
L
X
X
Terminate current Burst read cycle and start
new Burst read cycle
L
H
H
X
I/O
H
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| S29NS032JPLBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
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| S29NS064J0LBAW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
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