參數(shù)資料
型號: S29GL01GP13FAI010
廠商: SPANSION LLC
元件分類: PROM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述: 1G X 1 FLASH 3V PROM, 130 ns, PBGA64
封裝: 13 X 11 MM, 1 MM PITCH, FBGA-64
文件頁數(shù): 45/71頁
文件大小: 990K
代理商: S29GL01GP13FAI010
November21,2006 S29GL-P_00_A3
S29GL-P MirrorBit
TM
Flash Family
43
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8.5
Advanced Sector Protection Software Examples
Table 8.2
contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the
sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB
Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See also
Figure 8.1
for
an overview of the Advanced Sector Protection feature.
8.6
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP#/ACC is at V
IL
, the either the highest or lowest sector is locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes these methods:
8.6.1
WP#/ACC Method
The Write Protect feature provides a hardware method of protecting one outermost sector. This function is
provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection
method.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and erase functions in the
highest or lowest sector independently of whether the sector was protected or unprotected using the method
described in "Advanced Sector Protection/Unprotection" section.
If the system asserts V
IH
on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to
be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether
they were last protected or unprotected.
Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of the device
may result.
The WP#/ACC pin must be held stable during a command sequence execution.
Note
If WP#/ACC is at V
IL
when the device is in the standby mode, the maximum input load current is increased.
See
Table 11.6 on page 50
for details.
8.6.2
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control inputs to prevent unintentional writes when V
CC
is greater than V
LKO
.
Table 8.2
Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations
Unique Device PPB Lock Bit
0 = locked
1 = unlocked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
Any Sector
0
0
x
Protected through PPB
Any Sector
0
0
x
Protected through PPB
Any Sector
0
1
1
Unprotected
Any Sector
0
1
0
Protected through DYB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
1
0
Protected through DYB
Any Sector
1
1
1
Unprotected
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