參數(shù)資料
型號(hào)： S29CD032G0PFAN010
廠商： SPANSION LLC
元件分類： DRAM
英文描述： CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
中文描述： 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數(shù)： 84/93頁
文件大小： 1608K
代理商： S29CD032G0PFAN010
84
S29CD032G
30606B0 March 22, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Enter
Embedded
Erasing
Note:
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 26. DQ2 vs. DQ6 for Erase/Erase Suspend Operations
Erase
Erase
Resume
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
Suspend
Program
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
Status Data
VA
VA
t
OE
t
OE
Notes:
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation
is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY
is active one clock cycle before data.
4. Data polling requires burst access time delay.
Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings
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