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| 型號： | S29CD032G0PFAN010 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY |
| 中文描述： | 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 22/93頁 |
| 文件大?。?/td> | 1608K |
| 代理商： | S29CD032G0PFAN010 |
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22
S29CD032G
30606B0 March 22, 2004
A d v a n c e I n f o r m a t i o n
CE# Control in Linear Mode
The CE# (Chip Enable) pin enables the device during read mode operations. CE#
must meet the required burst read setup times for burst cycle initiation. If CE#
is taken to V
IH
at any time during the burst linear or burst cycle, the device im-
mediately exits the burst sequence and floats the DQ bus signal. Restarting a
burst cycle is accomplished by taking CE# and ADV# to V
IL
.
ADV# Control In Linear Mode
The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock
edge when CE# and ADV# are at V
IL
and the device is configured for either linear
burst mode operation. A burst access is initiated and the address is latched on
the first rising CLK edge when ADV# is active or upon a rising ADV# edge, which-
ever occurs first. If the ADV# signal is taken to V
IL
prior to the end of a linear
burst sequence, the previous address is discarded and subsequent burst transfers
are invalid until ADV# transitions to V
IH
before a clock edge, which initiates a new
burst sequence.
RESET# Control in Linear Mode
The RESET# pin immediately halts the linear burst access when taken to V
IL
. The
DQ data bus signal float. Additionally, the Configuration Register contents are
reset back to the default condition where the device is placed in asynchronous
access mode.
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the linear burst data on the DQ
data bus pin. De-asserting the OE# pin to V
IH
during a burst operation floats the
data bus. However, the device will continue to operate internally as if the burst
sequence continues until the linear burst is complete. The OE# pin does not halt
the burst sequence, this is accomplished by either taking CE# to V
IH
or re-issuing
a new ADV# pulse. The DQ bus remains in the float state until OE# is taken to
V
IL
.
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs
the system that the last address of a burst sequence is on the DQ data bus. For
example, if a 2-double-word linear burst access is enabled using a 16-bit DQ bus
(WORD# = V
IL
), the IND/WAIT# signal transitions active on the second access.
If the same scenario is used, the IND/WAIT# signal has the same delay and setup
timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# sig-
nal. If OE# is at V
IH
, the IND/WAIT# signal floats and is not driven. If OE#is at
V
IL
, the IND/WAIT# signal is driven at V
IH
until it transitions to V
IL
indicating the
end of burst sequence. The IND/WAIT# signal timing and duration is (See “Con-
figuration Register” for more information). The following table lists the valid
combinations of the Configuration Register bits that impact the IND/WAIT#
timing.
Table 7. Valid Configuration Register Bit Definition for IND/WAIT#
DOC
WC
CC
Definition
0
0
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on risiong CLD edge
0
1
1
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
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