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參數(shù)資料
| 型號： | S29CD032G0PFAN010 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY |
| 中文描述： | 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 34/93頁 |
| 文件大?。?/td> | 1608K |
| 代理商： | S29CD032G0PFAN010 |
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34
S29CD032G
30606B0 March 22, 2004
A d v a n c e I n f o r m a t i o n
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
, or WE#
= V
IH
. To initiate a write cycle, CE# and WE# must be a logical zero (V
IL
) while
OE# is a logical one (V
IH
).
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power-up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to reading array data on power-up.
V
CC
and V
IO
Power-up And Power-down Sequencing
The device imposes no restrictions on V
CC
and V
IO
power-up or power-down se-
quencing. Asserting RESET# to V
IL
is required during the entire V
CC
and V
IO
power sequence until the respective supplies reach their operating voltages.
Once, V
CC
and V
IO
attain their respective operating voltages, de-assertion of RE-
SET# to V
IH
is permitted.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S29CD032J0MQAN010 | 制造商:Spansion 功能描述: |
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| S29CL016J0JQFM030 | 制造商:Spansion 功能描述:FLASH PARALLEL 3.3V 16MBIT 512KX32 54NS 80PQFP - Trays |
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