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參數(shù)資料
| 型號： | S29CD032G0PFAN010 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY |
| 中文描述： | 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 24/93頁 |
| 文件大?。?/td> | 1608K |
| 代理商： | S29CD032G0PFAN010 |
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24
S29CD032G
30606B0 March 22, 2004
A d v a n c e I n f o r m a t i o n
Table 8. Burst Initial Access Delay
Figure 3. Initial Burst Delay Control
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles
Burst CLK Edge Data Delivery
The device delivers data on the rising of CLK. Bit 6 in the Control Register (CR6)
is set to 1, and is the default configuration.
Burst Data Hold Control
The device is capable of holding data for one CLKs. The default configuration is
to hold data for one CLK and is the only valid state.
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the burst access is immediately
terminated and the device defaults back to asynchronous read mode. Refer to
RESET#: Hardware Reset Pin
for more information on the RESET# function.
CR13
CR12
CR11
CR10
Initial Burst Access
(CLK cycles)
54D, 64C, 65A, 75E
0
0
0
0
2
0
0
0
1
3
0
0
1
0
4
0
0
1
1
5
0
1
0
0
6
0
1
0
1
7
0
1
1
0
8
0
1
1
1
9
CLK
ADV#
Addresses
DQ31-DQ0
3
DQ31-DQ0
4
DQ31-DQ0
5
Valid Address
Three CLK Delay
2nd CLK
3rd CLK
4th CLK
5th CLK
1st CLK
Four CLK Delay
Address 1 Latched
Five CLK Delay
D0
D1
D2
D3
D0
D1
D2
D0
D1
D2
D3
D4
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