參數(shù)資料
型號(hào): S1C88816D
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164
封裝: DIE-164
文件頁(yè)數(shù): 41/173頁(yè)
文件大小: 1411K
代理商: S1C88816D
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S1C88816 TECHNICAL MANUAL
EPSON
127
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter)
PRAD: 00FF80HD3
Controls the clock supply to the A/D converter.
When "1" is written: ON
When "0" is written: OFF
Reading:
Invalid
By writing "1" to the PRAD register, the clock
selected with the PSAD register is input to the A/D
converter.
When "0" is written, the clock is not input to the
A/D converter.
At initial reset, this register is set to "0" (OFF).
ADRUN: 00FF82HD7
Starts A/D conversion.
When "1" is written: Start A/D conversion
When "0" is written: Invalid
Reading:
Always "0"
By writing "1" to this register, the A/D converter
starts A/D conversion of the channel selected by
the CHS register, and stores the conversion result to
the ADDR register.
CHS0, CHS1: 00FF82HD0, D1
Selects an analog input channel.
Table 5.15.6.3 Selection of analog input channel
Input channel
AD7
AD6
AD5
AD4
CHS1
1
0
CHS0
1
0
1
0
At initial reset, this register is set to "0" (AD4).
ADDR0–ADDR9: 00FF84HD0, D1, 00FF83H
A/D conversion result is stored.
ADDR0 is the LSB and ADDR9 is the MSB.
ADDR0 and ADDR1 are assigned in D0 bit and D1
bit of the address 00FF84H. D2–D7 bits in this
address are always "0" when being read.
At initial reset, data is undefined.
PADC0, PADC1: 00FF28HD6, D7
Sets the priority level of the A/D conversion
completion interrupt.
Table 5.15.6.4 shows the interrupt priority level
which can be set by the PADC register.
Table 5.15.6.4 Interrupt priority level settings
PADC1
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
PADC0
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, this register is set to "0" (level 0).
EAD: 00FF2AHD7
Enables or disables the A/D conversion completion
interrupt generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
Valid
The EAD register is the interrupt enable register
corresponding to the A/D conversion completion
interrupt factor. When this register is set to "1", the
interrupt is enabled, and when it is set to "0", the
interrupt is disabled.
At initial reset, this register is set to "0" (interrupt is
disabled).
FAD: 00FF2CHD7
Indicates the generation of A/D conversion
completion interrupt factor.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
FAD is the interrupt factor flag corresponding to
the A/D conversion completion interrupt. It is set
to "1" when an A/D conversion is completed.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding interrupt
priority register is set to a higher level than the
setting of the interrupt flags (I0 and I1), an interrupt
is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an inter-
rupt generation, it is necessary to re-set the inter-
rupt flags (set the interrupt flag to a lower level
than the level indicated by the interrupt priority
registers, or execute the RETE instruction) and to
reset the interrupt factor flag. The interrupt factor
flag is reset to "0" by writing "1".
At initial reset, the FAD flag is reset to "0".
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