- 您現在的位置：買賣IC網 > PDF目錄98069 > S1C88816D 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164 PDF資料下載
參數資料
| 型號： | S1C88816D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164 |
| 封裝： | DIE-164 |
| 文件頁數： | 138/173頁 |
| 文件大?。?/td> | 1411K |
| 代理商： | S1C88816D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁當前第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁
S1C88816 TECHNICAL MANUAL
EPSON
59
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
s Receive error
During receiving the following three types of errors
can be detected by an interrupt.
(1) Parity error
When writing "1" to the EPR register to select
"with parity check", a parity check (vertical
parity check) is executed during receiving. After
each data bit is sent a parity check bit is sent.
The parity check bit is a "0" or a "1". Even parity
checking will cause the sum of the parity bit
and the other bits to be even. Odd parity causes
the sum to be odd. This is checked on the
receiving side.
The parity check is performed when data
received in the shift register is transferred to the
received data buffer. It checks whether the
parity check bit is a "1" or a "0" (the sum of the
bits including the parity bit) and the parity set
in the PMD register match. When it does not
match, it is recognized as an parity error and the
parity error flag PER and the error interrupt
factor flag FSERR is set to "1".
When interrupt has been enabled, an error
interrupt is generated at this point.
The PER flag is reset to "0" by writing "1".
Even when this error has been generated, the
received data corresponding to the error is
transferred in the received data buffer and the
receive operation also continues.
The received data at this point cannot assured
because of the parity error.
(2) Framing error
In asynchronous transfer, synchronization is
adopted for each character at the start bit ("0")
and the stop bit ("1"). When receiving has been
done with the stop bit set at "0", the serial
interface judges the synchronization to be off
and a framing error is generated. When this
error is generated, the framing error flag FER
and the error interrupt factor flag FSERR are set
to "1". When interrupt has been enabled, an
error interrupt is generated at this point.
The FER flag is reset to "0" by writing "1".
Even when this error has been generated, the
received data for it is loaded into the receive
data buffer and the receive operation also
continues. However, even when it does not
become a framing error with the following data
receipt, such data cannot be assured.
Even when this error has been generated, the
received data corresponding to the error is
transferred in the received data buffer and the
receive operation also continues. However, even
when it does not become a framing error with
the following data receiving, such data cannot
be assured.
(3) Overrun error
When the next data is received before "1" is
written to RXTRG, an overrun error will be
generated, because the previous receive data
will be overwritten. When this error is gener-
ated, the overrun error flag OER and the error
interrupt factor flag FSERR are set to "1". When
interrupt has been enabled, an error interrupt is
generated at this point. The OER flag is reset to
"0" by writing "1" into it.
Even when this error has been generated, the
received data corresponding to the error is
transferred in the received data buffer and the
receive operation also continues.
Furthermore, when the timing for writing "1" to
RXTRG and the timing for the received data
transfer to the received data buffer overlap, it
will be recognized as an overrun error.
s Timing chart
Figure 5.7.7.4 show the asynchronous transfer
timing chart.
相關PDF資料 |
PDF描述 |
|---|---|
| S1C88832F0A0100 | MICROCONTROLLER, PQFP128 |
| S1C88848D0A0100 | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
| S1C8F360F | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| S1D13305F00B | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
| S1D13305F00A | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S1C88848 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C8F360D411000 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| S1C8F360D511000 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| S1C8F360F413100 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| S1C8F360F513200 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。